| The enormous advantages of higher density in Integrated Circuits (IC) are well known; it results in faster circuits due to smaller parasitic elements, and more circuits per wafer due to smaller circuit sizes. Higher density can be achieved through either overlying successive patterns more precisely in the circuit or delineating smaller features. The former is more appealing, however, because it is pushing neither the physics of resolution of the patterning nor the physics of operation of the circuit.; The precise registration of successive patterns necessitates more accurate alignment between the consecutive fabrication steps, where alignment is defined as finding the best fit of the aerial (incoming) image to the existing structure. Achieving rapid and accurate alignment is one of the most crucial emerging challenges in lithography, especially under the wide variety of conditions brought about by different overlying films occluding the alignment marks. The problem is further exacerbated by planarizing processes such as chemical mechanical polishing (CMP) that reduce the topographical contrast used to view the marks, by asymmetric processes such as metal deposition, and by distortion of the wafer. These phenomena give rise to the displacement of the perceived position of the alignment marks, and can be categorized into (i) process-induced asymmetry of alignment signal, and (ii) wafer distortion.; To address the problems in the first category, we realize that the systematic variations of alignment signals is due to the changes in the parameters on the preceding process steps, which lead to a linear model for alignment signals. Subspace techniques in sensor array processing were subsequently utilized to construct this linear model from a set of alignment signals with pre-known positions, i.e., a learning set. The position of a new alignment signal was determined based on the fact that, if shifted appropriately, it would also fit into the model. The experimental results showed more than 70% improvement, corresponding to about 40nm reduction in alignment error, compared to the conventional methods that do not take into account the variations in the signals.; Even the perfect positioning of signals will not eliminate the problem in the global alignment scheme, where the positions of only a few sites on the wafer are measured and used to align all the sites. Techniques similar to those mentioned above were employed to learn the wafer distortion patterns from the overlay data of the prior wafers and compensate for them in the new wafers. The algorithm was applied to data from AMD and Motorola and results indicated more than 60% improvement in alignment accuracy for metal CMP test wafers. |
