Design and implementation of low power phase locked loop circuits for wireless applications

The wireless market has experienced an exponential growth over the past decade. To sustain this growth and increasing demands of new wireless standards, the cost, battery lifetime, and performance of wireless devices must all be enhanced. One of the most critical components in a wireless transceiver is the frequency synthesizer. With the advancement of radio frequency (RF) technology and requirement of low power, new RF architectures are needed. A phase locked loop is a typical example of a frequency synthesizer. In this thesis simple low power phase locked loops are designed and implemented for analog and digital systems.;The power consumption is a critical factor in many wireless devices. In this research, the objectives are to reduce the number of switching activity in a design and to operate the devices in the subthreshold region to reduce power consumption of the circuit.;This research analyses the phase locked loop (PLL) design for different nanoscale CMOS subsystems. The power consumption in these CMOS subsystems are evaluated for different CMOS transistor technology nodes. A single balanced topology mixer is implemented as a frequency divider circuit in the analog PLL design. A digital low power PLL consisting of full adder circuit is also designed and tested with different full adder circuits for low power consumption. Analysis of all the PLL designs and its individual components for power consumption gives us insight in choosing the simplest low power circuit.;Throughout this work, low-power has been achieved by both architectural as well as circuit techniques. All the PLL designs are simulated and tested for their proper functionality and finally they are implemented on-chip for AMI 0.5mum technology. This research work gives a detailed analysis of the PLL design and implementation, by considering most of the factors such as low cost, low power, high performance and high frequency for RF wireless applications.