Research And Design Of Key Technology Of CMOS Phase Locked Loop

In order to adapt to the increasing of people's material and cultural needs,wireless communication system in People's Daily life gradually occupy more important position,with the advent of the era of 5 g millimeter wave,wireless communication systems use desktop module design is increasingly important,as an important module in the transceiver,phase-locked loop bearing vibration frequency of the up and down the pros and cons of its performance severely restricts the whole transceiver system of received signal.CMOS system has its natural advantages because of its high cost and low integration,so the research and design of the key technology of CMOS phase-locked loop is of great significance.In this paper,based on CMOS process,completed the voltage-controlled oscillator,frequency divider,decimal phase-locked loop design,first of all,we discuss the historical development of phase-locked loop first context of research and the research status at home and abroad,analysis of the current research and the deficiency of the existing problems,and finally to CMOS phase-locked loop has carried on the related research and discussion,the theory of system characteristic of CMOS phase-locked loop are analyzed in detail and performance indicators,finally analyzes the design of each module in the phase-locked loop points and problems needed to resolve,finally give the discussion above module design completed the following sections:For,the closer it gets to the millimeter wave frequency flicker noise of CMOS devices,the more obvious,with the reduction of process dimension flicker noise greatly worsened nearly at a voltage-controlled oscillator noise area,this paper analyzes the traditional tail current source type is a Class B flicker noise VCO formation mechanism,and according to the scholars analyze the improvement of defect,the innovative use tail resistive voltage controlled oscillator,eliminates the produce large amounts of flicker noise source,to reduce the spread of flicker noise;Secondly,according to the theory of noise transfer function,the transfer function of flicker noise is analyzed,and the transfer function of flicker noise can be reduced by waveform shaping.Therefore,the impedance problem in the case of broadband is analyzed,and the flicker noise is effectively reduced by making the quadratic impedance present within a certain bandwidth.For 5.8GHz moving target detection radar,the design of low power consumption requires low power consumption of phase-locked loop,and the frequency divider is a large part of the phase-locked loop.Therefore,after comparing the CML frequency divider and TSPC frequency divider,the design of a lower power octave containing the working frequency of the VCO is selected.For 24 GHZ car radar application scenario for the broad,we research and design the24 GHZ decimal phase-locked loop,designed and adopted a digital frequency automatic control link,the subband,wide frequency band,under the condition of open loop calibration subband priority,and then began to close the frequency calibration phase-lock link,the voltage-controlled oscillator structure of loop noise,frequency divider with CML and TSPC work together,the low frequency part with a digital frequency divider and multimode frequency divider,DSM(Delta Sigma Modulator)by tuning multimode frequency divider to achieve the effect of the decimal frequency division.