Research On FPGA-based V-by-One Video Transceiver System And HDMI Data Conversion

V-by-One,as a Point To Point(P2P)ultra-high-definition digital video image transmission technology,can support 1920*1080 and 3840*2160 resolutions transmission,and the maximum single-link clock frequency is 4Gbit/s.V-by-One adopts multi-channel differential serial transmission,8B/10 B encoding,data scrambling,Clock and Data Recovery(CDR)and other technologies to reduce Electromagnetic Interference(EMI),also it can transmit lossless picture quality of video images.However,the video image interface of the V-by-One protocol is not compatible with the currently and commonly used display interface.Therefore,to obtain images transmitted by V-by-One,it is necessary to convert the V-by-One protocol format data into a common image interface format data.High Definition Multimedia Interface(HDMI)based on Transition Minimized Differential Signaling(TMDS)technology has good compatibility,can transmit all-digital uncompressed audio/video signals,and occupies a dominant position in the audio and video transmission interface in the field of consumer electronics.Based on the V-by-One technology,this paper starts research on the subject.Through the research on the V-by-One single link transceiver and protocol,the V-by-One transceiver system is designed on the Field Programmable Gate Array(FPGA)device,and the V-byOne protocol is converted into a general High Definition Multimedia Interface(HDMI)data format.The entire V-by-One transceiver system mainly studies the V-by-One data transmission and reception system with 1920*1080 image resolution,pixel clock of 148.5Mhz,dual channels,and 4-byte mode;including data sources,serial-parallel conversion,and sampling,8B/10 B codec,data scrambling and descrambling,data parsing module,and DDR3 storage unit.The specific research contents are as follows:First,the V-by-One transmitter realizes the transmission of high-speed serial differential data.A single-channel RGB digital image data can be converted into dualchannel,4-byte mode data by the data source module;8B/10 B encoding circuit and scrambling circuit can encode and scramble the data;and parallel data can be converted into differential image data through parallel-to-serial conversion and TTL signal to differential signal circuits.Second,the V-by-One receiver realizes the reception of high-speed serial differential data.The differential data to TTL signal circuit converts the differential data into a singleended TTL data.The CDR clock recovery circuit is used to extract the link clock from the high-speed serial data and the clock is used to realize serial-to-parallel conversion and sampling;the serial-to-parallel data performs 8B/10 B decoding,data descrambling,and DDR3 storage,and finally sends it to the HDMI interface for display.Third,convert the data into HDMI interface signals.The data of the DDR3 storage unit is sent to the HDMI data conversion chip SIL9134,and the SIL9134 chip is configured,which mainly includes the device address,register address,and configuration data.Fourth,the 8B/10 B codec is implemented using combinational logic circuits based on characteristics of encoding data.The scrambling and descrambling circuit adopts the parallel structure of LFSR,which is more suitable for the parallel processing characteristics of FPGA.The DDR3 control unit is realized by combining FIFO and user logic to achieve data storage and image mirroring.After verification,the system can correctly implement data transmission,reception and data conversion.