Key Circuit Design Of High-Speed DDR3 I/O Unit

With the rapid development of processor performance,the performance requirements of memory interface circuits are also increasing.Nowadays,DDR3 is a high-speed interface technology that is widely used,and DDR3 IO is a key technology for high-speed transmission.The main challenges faced in designing DDR3 IO interface circuits are as follows: in the first place,with the decrease of interface voltage,which brings higher requirements for the driving capacity of the transmitter.Furthermore,due to the increase of the frequency of the output signal,the board-level transmission lines is easily reflected at the terminal.Finally,the thickness of gate oxide is getting thinner and thinner,which puts forward higher requirements for ESD protection circuit and so on.This article addresses the above issues and studies the key circuits of DDR3 IO cells.The main tasks include:(1)In order to realize the high-performance design of IO interface circuit,the transmitter adopts on-chip ODT circuit design with large size MOS tube driver,which makes the output signal produce large output current to drive large capacitance loads.In order to improve the readout speed of the transmission signal,the receiver employs a two-stage operational amplifier as a comparison readout circuit to quickly and accurately compare the amplified output signals.Through the design and optimization of the on-chip transceiver ODT circuit and the two-stage op amp circuit,the data rate of the IO interface circuit can reach 2133 Mbps,which meets the design specifications and design requirements of JEDEC.(2)In order to improve the signal integrity of the IO interface circuit,a suitable topology is adopted to reduce or prevent the reflection of the transmission line.To improve the reflection of the transmission line,the data signal is transmitted through the series termination topology,and then the other controls and address signals are connected in parallel connect topology to reduce transmission line reflections.Meanwhile,the off-chip OCT calibration unit is used to calibrate the on-chip ODT internal resistance.The programmable on-chip ODT structure can generate an appropriate on-chip internal resistance to improve output signal transmission quality.After adding 7.5nH of inductance both on the power supply and on ground,the series-terminated eye diagram data window can be up to 228 ps and the jitter is 33.9ps;the parallel termination eye diagram data window can be up to 133 ps and the jitter is23.3ps.(3)In order to improve the reliability of the IO interface circuit,the reverse clamp diode,resistance buffer current limiting,GGNMOS,GDPMOS and the RCNMOS are combined together to quickly discharge the ESD current.In the ESD HBM mode,up to4 KV ESD voltage is supported,and the reliability of the design is good.