DDR3 Design And Implementation Based On FPGA

In recent years, the high speed digital systems improve constantly the bandwidth requirements. FPGA-based systems frequently require an external memory interface to buffer data that exceeds the capacity of the FPGA’s internal memory. This memory interface can often dictate overall system performance. In addition to higher performance, the design of memory controller also needs to be flexible and easy to implement. The memory control logic becomes gradually more and more complex, the interface design is more and more challenging With the higher speed and capacity of the memory.The subject in this paper is a design of DDR3 memory controller and interface based on FPGA, mainly starting from two aspects of timing control logic and Leveling function, launched a research and design to satisfy the requirement of high performance. The major works are as follows:First of all, this paper has put forward the necessity of the design of DDR3 Write Leveling technology due to FLY- BY topology from the characteristics and function of DDR3, and analyzed deeply DDR3 complex working process and the relevant orders. And then, the overall architecture design of the various modules in DDR3 controller based on FPGA has carried on in the project of high-speed high-performance processing board, and the implementation details of design at 400 MHZ and 800 MHZ clock frequency has been given, expecting high efficiency using the data transfer rate of DDR3-1866. Aiming at the flight time skew between the clock signal and DQ/DQS from FLY- BY topological structure, we further elaborated Write Leveling technology principle. Combining with signal integrity and timing analysis of the key signal in the process of Leveling, the specific realization method of Leveling that based on FPGA physical interface and implementation of relevant algorithm in Write Leveling process has been given. Finally, with the help of the Xilinx on-chip logic analyzer that called ChipScope, completed the board level validation and debugging of DDR3 Leveling technology design, through the hardware platforms on Xilinx ML605 development board and high-speed high-performance processing board.After DDR3 system based on Kintex- 7 series FPGA running a period of time, through the ChipScope to monitor some of the key signal, finally succeeded in achieving the 800 MHz high-speed transmission rate, and verified in a development board and a practical system. The algorithm is innovative and has the engineering application value. It has provided experience for the design optimization in Leveling technology in the future.