FPGA High-speed DDR3 Memory Interface Design

With the increasing development of 5G communication?mega data computing?AI and other emerging fields,Field Programmable Gate Array(FPGA)shows greater potential in these applications with high flexibility and good versatility,meanwhile,there is a new opportunity to develop domestic FPGA technology.In the applications of data processing based on FPGA,storage capacity always needs to be extended by external DDR memory device with high data transmission rate and large capacity,accounting for the limited resource of RAM inside FPGA.DDR3 is the third generation of DDR memory which is widely used in hardware system,and the data transmission rate is further improved.It can achieve the transmission rate about 2133 Mbps or even better in server applications.The high-speed data access between the FPGA and DDR3 memory is realized through dedicated memory interface IP embedded in the FPGA,which processes signal timing and data synchronization.The demand for data bandwidth in high-speed interconnect is increasing.As an important part of the FPGA technology in high-speed interconnect,the performance of the DDR3 memory interface has also become a key indicator of chip.It is an important and difficult point in memory interface design to achieve higher transmission speed while satisfying the critical timing specification.On the basis of studying the specification of DDR3 memory and the related theories about high-speed interface,this paper proposes the semi-custom DDR3 physical layer interface solution in FPGA chip,and accomplishes the design of read path,write path,command/ address path,clocking architecture and initialization & training sub-module based on specific macrocell.The functions of specific macrocell are simulated first in the subsequent validation,then,a mixed-signal simulation platform is constructed to complete the system-level verification of DDR3 physical layer.In this paper,traditional solution of FPGA memory interface is introduced,afterwards,it points out challenges to be solved in high performance design of memory interface,that is,the difficulty in data synchronization caused by the compression of timing window with high data rate and frequency mismatch between FPGA core and DDR3.Gearbox,a data transfer structure with adjustable ratio,is used to realize frequency and data rata matching between FPGA core clock and memory clock.In order to solve the challenges of data synchronization,dedicated clock synchronization module is designed to generate clocks during transmission.The initialization and training module will execute the timing training in data path by read calibration and Write Leveling.This mechanism can ensure the timing specification and achieve robust data synchronization between FPGA and DDR3 memory.This paper derives from a project of FPGA chip,and the DDR3 physical layer interface can be used as IP.1600 Mbps data rate can be achieved without considering the signal integrity.Dedicated macrocell are designed on the strength of 28 nm specific cell library and will be integrated in FPGA as hard core.