36-channel Target Echo IF Simulator Based On FPGA

In recent years,the function of radar has become more and more diversified.However,debuging such radar in the real target environment not only fails to guarantee safety but also increases the R&D cost.In this context,radar simulator was born.Radar simulators can simulate echo signals with information of target distance,velocity,and angle in real time.By simulating noise and clutter and adding them to the signal,the simulator can simulates the real environments.According to the actual application requirements,this paper designed and implemented a 36-channels target echo IF simulator based on FPGA.The 36-channel target echo IF simulator receives the target parameter information from the PC interface.Then it transmits the information to the PowerPC for calculation and quantification.Finally,the FPGA outputs echo signals simultaneously with the CPI and PRF pulse beats,which provided by the radar system.The design and implementation process of this paper is mainly divided into the following phases.The first phase analyzes the task requirements and working mode of the simulator,designs the logical relationship of the main signals between the boards and the workflow of the system.The second phase analyzes the versatility of the IF simulator,studies the principle of the echo generation model,and simulates and verifies the echo generation scheme in Matlab.The third phase designes the hardware scheme of the simulator system,completes the chip selection,schematic drawing and PCB plate making.The fourth phase writes the code of the software program in the ISE.Verilog code is used to generate echo signal and output synchronously.The C code of PowerPC is used to receive the target parameter information,and transmit the information to FPGA after calculating.The fifth phase debugs the simulator with a circular array radar system.Finally,the target information obtained from the radar interrupting interface is consistent with the set parameters,which verifies that the IF simulator meets the design requirements.At the same time,a lot of interfaces and designs are reserved in the hardware scheme of the card,which provides the hardware foundation for the subsequent system upgrade and function expansion.