Research And Design Of SRAM-Type Computing In Memory Circuit For Competitive Neural Network

With the rapid development of artificial intelligence,the amount of data it needs to process is exploding.However,the traditional von Neumann architecture can hardly meet the demand for real-time processing of massive data due to the storage wall bottleneck.In order to break this bottleneck,the idea of computing-in-memory was proposed,i.e.,to embed computational logic in the storage unit to solve the problem that the data transfer speed is limited by the bus bandwidth.Artificial intelligence is processed by artificial neural networks for practical tasks.In pattern classification,competitive neural networks have simple structures and good classification effects,but their hardware implementation is still limited by the von Neumann bottleneck.To this end,this thesis proposes an SRAM-type computing-in-memory circuit for competitive neural networks,the main research work is as follows:(1)This thesis proposes a 10 T SRAM cell that can realize the XNOR operation to address the mode overlap and write interference problems faced by the current research on the computing-in-memory.This thesis proposes a 10 T SRAM cell that can implement the XNOR operation to solve the mode overlap problem caused by the dot product operation,and the decoupling of its read and write ports can solve the write interference problem in the process of computing-in-memory.To address the computational linearity problem,this thesis proposes a lateral-inhibition circuit based on the ”winner-take-all” mechanism,which can greatly reduce the impact of computational linearity on computational results by using the ”winner-take-all” competition method.(2)The traditional competitive neural network uses all neurons to compete simultaneously to obtain computational results,and the classification accuracy is related to the number of neurons.In this thesis,a combined voting mechanism of competing neurons is proposed,which can effectively improve the classification accuracy and robustness of the computing-in-memory circuit.In addition,the two-by-two competition of adjacent neurons can suppress the computational consistency problem caused by input pulse distortion.(3)This thesis implements a circuit design and layout design of an SRAM-type computingin-memory chip for competitive neural networks based on a 55 nm CMOS process.In order to verify the pattern classification function of the computing-inmemory circuit,a classification test is conducted using MNIST dataset.The test results demonstrate that the 10 T SRAM-based computing-in-memory circuit with combined voting mechanism has a satisfactory classification effect.By compromising the area overhead and classification accuracy,the core storage array size of the computing-in-memory circuit in this thesis is 64×90bit,and its classification accuracy can reach 98.62%,throughput can reach 576 GOPS,and energy efficiency can reach 533.3 TOPS/W.