High Performance Low Power Embeded SRAM Design And Optimization

Accompanied with the lasting increasing of the IC's intensity and operating frequency as the Moor's law, high performance and low power designs become the mainstream of chips.The memories have taken an absolutely large part of area on microprocessors, especially in SoCs, and the tendency is still going on.The consequence is the increase of length of wordlines and bitlines in memories, and delay and power.The designing of high speed and low power memories are going to play an significant role in developing of IC more and more.The YHFT-DX is an 8-issue VLIW DSP designed by school of computer in National University of Defense Technology. YHFT-DX integrates 1MB L2 Cache whose frequency is 300MHz. Aiming at the design demands of YHFT-DX, the thesis is trying to make a deep study of SRAM's designing technologies. The main contributions are as follows.1. The analysis and optimization of embedded SRAM.The thesis emphasizes on the discharging of bitlines while the wordlines are actived and investigates the method of controlling discharging based on the replicating curcuit and the self-timing circuit.We introduce an effctive approach of contrlling the bitlines'discharging delay and swing .The simulating consequence manifests that the access time of SRAM has been lessen by 31% and the average power also has been decreased by 25%, compared with the original SRAM.2. The thesis also explored some particular methodologies to speed up the simulation of large scale SRAM, and simulated the SRAM we designed and optimized both in the circuit level and in the layout level.Then we analyzed the process of building the timing library of SRAM and speed up the process by bringing in Perl language.3. We also tested a bank of ready-to-tapeout SRAM with a particular scan-chain testing structure, referring with the traditional conception of scan test. The consequence affirmed the correct function of our SRAM and it bears a limit operating frequency of 700MHz under TT corner and a limit operating frequency of 500MHz under SS corner.The scale of the SRAM designed and optimized in the thesis is 1MB, the delay and average power of its partition is 1.34ns and 19.8mW under the TT corner. The research of SRAM provides a practical solution for implementing the L2 Cache of YHFT-DX microprocessor and lays a foundation for further investigation on upgrading the performance of embedded large scale SRAM.