Computing In-Memory Design Based On Double Word Line And Double Threshold 4T SRAM

The rapid development of the technology to promote the new technology has been widely applied to human daily life,however,the amount of data applications needed to be addressed also will be increased sharply.Because the development trend of memory technology cannot expand as quickly as computing performance,it has led to the so-called von-Neumann memory wall.In order to solve the "memory wall" and a series of problems it brings,scholars have proposed a new type of computing architecture-computing in-memory architecture.This paper describes the background and current development of the semiconductor industry,and proceed from the SRAM(Static Random Access Memory)memory cell,and introduces its working principle and operation steps in detail.Subsequently,in the storage system based on SRAM,the realization principles and operation steps of several computing in-memory technologies were analyzed and summarized.On the basis of summarizing the advantages and disadvantages of several computing in-memory technologies,this paper proposes a dual-word-line dual-threshold 4T SRAM memory cell,and optimizes the peripheral circuit of the storage system based on this cell,so that the designed SRAM system has a traditional SRAM memory access and emerging computing in-memory(CIM)application two modes.In SRAM mode,the storage system mainly performs read,write,and hold operations,and in CIM mode,it mainly performs BCAM(Binary Content Addressable Memory)and basic logic operations.During BCAM operation,the bit line is pre-discharged to a low level,a group of search data is input,by BCAM auxiliary decoding circuit decodes and controls the respective transmission tubes open off.If the search data is different from the stored data,there is always a storage node charging the bit line.After,the final matching result can be outputted and compared with a reference voltage by detecting the voltage change of the bit line SA(Sense Amplifier),and '1' is a match.'0' is a mismatch.In the basic logic operation,one row of data and the last row of stored data is selected through the decoding circuit for operation,output circuit outputs the operation result and a gate circuit composed of SA.In the 65 nm CMOS process,compared with the 6T storage cell,the area of 4T storage cell is reduced by about 25%,compared with the single-line 4T storage structure,the double-line 4T storage structure can save about 47% of the read power in VLSI applications.