Research On SRAM In-memory Computing Reliability

Artificial intelligence,machine learning,and similar technologies have changed society in many aspects.However,such data-intensive applications impose a burden to the von Neumann architecture due to the frequent data exchange between memory and arithmetic logic unit,leading to increased energy consumption and reduced throughput of the entire computing.To overcome the limited bandwidth imposed by these traditional von Neumann structures,the concept of in-memory computing(IMC)was proposed.Although multirow read is essential to achieve static random-access memory(SRAM)inmemory computing,it may lead to the decrease of the stability of IMC,undermine read destruction,circuit linearity and computational consistency across columns.This paper investigates the causes of nonlinearity and inconsistency.Based on detailed analyses,a cascade current mirror(CCM)peripheral circuit is proposed.Only four transistors are added to each bit line(BL)for voltage clamping and proportionally mirroring the read current.In addition,a 6T SRAM cell with double word lines operating with the CCM further reduces the delay and improves consistency.To verify the effectiveness of the proposed design,a 4 Kb SRAM was implemented in 28 nm CMOS technology.The measurement results demonstrate that the proposed CCM can reduce the integer nonlinearity by up to 70% at 0.8V supply,and computational consistency is substantially improved by 56.84% at 0.9V supply.In addition,this paper verifies the performance improvement through classification using a convolutional neural network,achieving 91% accuracy in MNIST,and 86% accuracy in CIFAR-10.The CCM circuit proposed in this paper can be combined with a variety of IMC techniques to greatly improve the linearity.