Research On Encoding Compression Method In SoC Test Data

With the rapid development of the information age,and the market demand for electronic equipment is constantly rising.As the core of electronic equipment,the demand for integrated circuits is also growing with each passing day.The consumer market requires more functions of integrated circuits and smaller size.It is necessary to increase the number of embedded transistors per unit area of the chip by increasing the degree of chip integration to meet the needs of the consumer market.The advent of system on a chip has brought a qualitative leap for the development of integrated circuits,which has greatly improved the integration of the chip,so that the chip can be applied to core equipment in aerospace,military,medical and other industries.Once there is a problem with the chips on these core devices,the consequences are incalculable.Therefore,integrated circuit testing technology is the most effective way to ensure the high quality of chips which has become one of the hot topics of research by industry scholars.SoC chip needs to be tested with extremely large test data due to its high level of integration.A large amount of test data will cause two problems: One is the long test time and high test cost,and the other is that the test cannot be performed normally when the amount of test data exceeds the storage capacity of the automatic test equipment.The test data encoding compression method can perform lossless compression on the test data without changing the internal structure of the chip to alleviate the above problems.This thesis focuses on the subject of "SoC test data encoding compression",and proposes two test data compression schemes.the main contents are as follows:(1)Based on the test data compatible compression technology,this thesis proposes a code word count compression method.This method digs for the positional relationship between compatible data blocks,and converts the number of continuously compatible data blocks into corresponding code words by using the continuity of the position of the compatible data blocks.The code word of the method is in a one-to-many mapping relationship with the original data block,which is equivalent to secondary compression on the basis of compatible compression,so this scheme has a good compression effect.(2)Based on the run-length coding compression technology,a minimum runchanging point compression method is proposed.In this method,the test set is first grouped according to the same number of vectors.Use the overlapping relationship of vectors run changing range within the group to merge the run changing points.The run positions of all test vectors in the group are represented by one vector.The MRCP compression method breaks through the limitation of the traditional code compression that requires the use of code word suffixes to represent the run length.Compared with traditional run length compression,the code word is greatly shortened.This thesis is based on the MinTest test set,and related experiments are conducted for the ISCAS 89 standard circuit.The experimental results show that the two test compression schemes proposed in this thesis have good compression effects.Comparing the two schemes with other similar schemes,the compression effect is also better than other similar schemes to varying degrees.The two schemes proposed in this thesis can effectively alleviate the conflict between large test data and limited ATE memory and bandwidth,and reduce test costs.