Research On Built-off Self-Test For System-on-a-Chip

With the rapid development of the System-on-a-Chip (SoC) technologies, and the increase in integration and complexity of chips, the amount of data required in the test of large-scale integrated circuits is increased significantly. However, the storage capacity, frequency and bandwidth of the traditional automatic test equipment (ATE) are limited. This results in longer test time, and more high cost in the SoC test. These problems might be solved by the replacement of advanced ATE, but it will lead to an increase in the cost of test equipment.This dissertation aims to solve the key problems due to the great volume of test data generated in the SoC test, by studying the relationship between two codewords, the characteristics of the fixed-length coding and the variable-length coding, and the division principle in the original test data, etc.The main contents of this dissertation include:(1) Two schemes of test data compression based on sharing-prefixed code and its special form, namely sharing-run-length code, have been developed, by exploring the relationship between consecutive runs. The dependency of the codewords on each other is implemented with these two schemes. As a consequence, the length of the following codewords will be reduced to enhance the compression effect by distributing the length of latter codeword to the former codeword.(2) Two test data compression schemes, hybrid fixed-plus- variable -length coding, have been analyzed, combining fixed-length and variable-length coding. They implement the combination of the merits in the codeword level and the way of coding, respectively. The former scheme has the flexibility of the fixed-length coding and decoding simplicity of the fixed-length coding. The compression effect of the latter is no longer limited by the number and length of runs in the original test data, which causes reduced encoded data. Hence, the compression ratio will be increased.(3) A selective output inversion technology has been proposed after exploring the relationship between the coding scheme and the test scheme. Three implementation approaches of the circuit structure are introduced. This technology takes the coding scheme and the test scheme into account together rather than considers them independently. By applying this technology, data can be compressed easily. The experimental results show that this technology can improve 17.28% in compression ratio for Golomb code.(4) A new division principle has been investigated, by taking both continuous series and reversal series into account. This overcomes the shortage of the traditional division principle which is limited by the types of runs. Using the new division principle can decrease the number of divisions. Then, a test data compression scheme based on the logic operation between adjacent bits has been proposed. The scheme turns all series into all 0 series so as to decrease the complexity of encoding. The experimental results show that this technology can improve the compression ratio by 7.02 % in comparison with FDR.(5) The original test data can be re-divided by 2 to the power of integer according to the successful coding characteristics of the LFSR, whose length equals to the power of 2 every division. In the new test approach, the numbers of specific bits in these test vectors are very close. Hence the encoding efficiency can be enhanced in the process of LFSR. Experimental results show that this scheme can improve 2.32 % in compression ratio than hybrid coding.