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Research On Data Compression Techniques In SoC Test

Posted on:2013-04-23Degree:MasterType:Thesis
Country:ChinaCandidate:L J WangFull Text:PDF
GTID:2248330377960734Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
The emergence of the System-on-a-Chip (SoC) brings a revolution to thedesign of the Integrated Circuits, it promots the development of the electronicindustry. In many fields, such as industry, communication, medical treatment,military, space and so on, a trivial SoC fault might causes serious losses, so moreand more researchers begin to focus on SoC test.With the rapid development of the SoC technologies, and the increase inintegration and complexity of chips, the amount of data required in the test oflarge-scale integrated circuits is increased significantly. However, the storagecapacity, frequency and bandwidth of the traditional automatic test equipment (ATE)are limited. This results in longer test time, and higher cost in the SoC test. Theseproblems might be solved by the replacement of advanced ATE, but it will leads toan increase in the cost of test. Because data compression techniques can resolveabove problems effectively, this thesis does an in-depth research on this field.The thesis introduced the related theoretical basis, summarized SoC self-testmethods and data compression technologies. At the beginning, two mainstreamself-test methods, BIST and BOST, are illuminated. After that, this thesis describedthe data compression technologies based on coding, introduced classic schemes,coding rules, characteristics.In order to improve the compression ratio, a new scheme of test datacompression and decompression, Subtraction Run-length coding is put forward.This scheme explored the relationship between consecutive runs, it settled thediscrete problem of code. Based on the traditional variable-length coding, the thesisused subtraction to reduce the length between two runs. there may be threesituations: if the later run-length smaller than the former, Original Run-lengthcoding is used; if two lengths are equal, the later run-length can be replaced only“01”; if the later run-length larger than the former, Subtraction Run-length codingis selected.This scheme was run in the larger scale sequential circuits of ISCAS89,the experiment result indicated that the compression ratio increase significantly. Tofurther demonstrate effectiveness, compared the average of the compression ratiobetween this scheme and traditional variable-length coding, it achieved7.72percent more than Golomb,2.21percent more than FDR.In addition, it has the availability and excellent prospects for simple circle structure and low areaoverhead.
Keywords/Search Tags:System-on-a-Chip, BIST, BOST, encoding compression, run-length, Subtraction of Run-length
PDF Full Text Request
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