Research On Test Vectors Compression Based On Run-length Coding

With the development of integrated circuit manufacturing process, the transistorsintegrating on a chip is more and more, feature is more and more powerful, whichbrought great convenience to the production and life. As the SoC integrationincreasing the amount of test data is rapidly increasing, which brought great pressureto the ATE memory, but also extended testing time, increased the cost of testing. Howto effectively compress the test data has become a hot issue in present. This paper isthe focus on test data compression issues.Test data compression technology is a key technology in the SoC test. Thisarticle describes some of common compression methods used in test data compressiontechnology, focuses on run-length encoding and its characteristics were analyzed.Because run-length encoding is a simple implementation method, and its hardwareoverhead is small, many improvements in compression techniques are based onrun-length encoding. Two improved compression schemes are referred to in thisarticle are based on characteristics of run-length encoding.Scheme one using difference method between adjacent vectors compress test data.In the past, although some scholars proposed a difference method, but did not give aspecific difference scheme, the result of difference is not clear. Here in this article aconcrete difference scheme is proposed: first test vectors sorted by vectorcompatibility between rows, and then by the column fill don’t care bits X, lastdifference vectors between adjacent vectors. After above steps for test vectorprocessing, test set will be more0, the length of0run-length is increased, which issuitable for FDR single run-length encoding.Scheme two resort test vectors to compress test data. Through research found that,with the two run-lengths in dual run-length encoding, try to increase the longrun-length and shorten the short run-length, which can improve the compression rate.To use this feature, this article defined a new compatibility to resort test vectors. Inthis scheme, assuming all test vectors to form a matrix by rows, each line represents atest vector，firstly, columns of the number of1s more than the number of0s will beinverted, under the new definition compatibility, and then the columns will berearranged in order of priority with the compatibility of size. Through this method,the length of a single run-length can be increased and the total number of run-lengthcan be reduced, the number of the scan shift transitions can be reduced simultaneously.Both of the two proposed compression schemes made a related experiment,experimental results show that these two schemes have achieved good compressioneffect, scheme two not only improves the data compression rate, but also reduce thetest power consumption.