Design And Realization Of A Frequncy Synthesizerapplied To The Caesium Atomic Clock

Modern wireless communication and navigation systems rely heavily on stable frequency source systems for reference and positioning,and atomic clocks are mainly used for this purpose.The miniaturized atomic clock device is a hot topic.The frequency synthesizer used in atomic clock is an important part of atomic clock equipment,which is of great significance to the miniaturization of atomic clock equipment.Compared with the general frequency synthesizer chip,the frequency synthesizer used in atomic clock devices requires higher frequency precision and better phase noise.In this thesis,the application in the study of frequency synthesizers of cesium atomic clocks,implements one can output 3417MHz low noise,low power consumption and the accuracy of frequency resolution can be reached as the following 5 mHz??PLL type decimal frequency synthesizers chip.It consists of phase frequency detector(PFD),charge pump(CP),voltage-controlled oscillator(VCO),dual-modulus prescaler,programming divider,sigma-delta modulator and SPI.Fabricated in JAZZ 0.18?m RF CMOS,the chip occupies 2.2 mm~2.This dissertation completes the design of architecture and circuits of the frequency synthesizer with simulation and measurement.The major contributions of this dissertation are as follows:1)Basic theory analysis:the system analysis of the frequency synthesizer for the cesium atomic clock was analyzed,and the design goal was given.2)Circuit design:according to the atomic clock frequency synthesizer chip low power requirements,design a model to realize frequency programming and implementation as?delta FSK modulation frequency synthesizers.In the design of the unit circuit,a low-gain,low-noise,low power consumption VCO with low gain and frequency temperature compensation is designed.The frequency divider adopts high speed dual mode frequency divider and programmable frequency divider to realize the coverage of frequency with the requirement of system power consumption.The linearization design technique is used to reduce the influence of the fractional noise on the overall noise of the synthesizer.3)Layout design:according to the experience of engineering design,layout design criterion of every unit are expounded,including the powe line,isolation,the symmetry of the device and high frequency signal line,ESD protection,etc.Finally,the layout design was completed and the flow verification was carried out.4)Test analysis:This thesis describes the chip test situation.The chip is packaged by QFN20 and tested on the PCB.The test results of the chip show that the frequency synthesizer can lock in 3417MHz and realize the frequency accuracy of less than 5mHz.The minimum power consumption is 14.5 mA.The phase noise of frequency@100KHz is-87dbc/Hz in integer mode,-78dBc/Hz in??mode,which basically meets the requirements of cesium atomic clock system and has low power consumption.