Research And Implementation Of Video Image Processing Based On FPGA

Digital image processing generally refers to various methods of image processing by computer or new hardware microprocessors,Digital image processing includes image enhancement,image restoration,image reconstruction,image analysis,pattern recognition,computer vision^[1].As a branch of image reconstruction,image scaling plays an indispensable role in the field of digital image processing,and is widely used in medical,monitoring,machine vision and other fields.The core of image scaling is image interpolation algorithm.The traditional image interpolation processing technology is mainly based on software platform,and generally runs on the PC of windows system.Although the main frequency of PC is relatively high nowadays,it is based on the serial processing method of software in image processing,which can not meet the demand in the situation of high real-time requirements.Therefore,how to implement the image interpolation algorithm in hardware and need fast computing speed,meet the real-time requirements,and meet the requirements of high bandwidth has become an important topic of image processing research.This paper proposes a video image processing method based on FPGA,FPGA can ensure a higher processing speed than PC software platform at a very low main frequency.The pipeline processing technology of FPGA can output an image after operation in each clock cycle,and realize complete parallel processing.Based on the in-depth study of the traditional interpolation algorithm,this paper uses MATLAB to simulate each interpolation algorithm,weighing the chip hardware resources,the complexity of algorithm implementation and the effect of algorithm implementation,and finally selects the bilinear interpolation algorithm to complete the implementation on FPGA.The key of the system design lies in the hardware implementation of bilinear interpolation algorithm and the division and coordination of each module,which makes the scaling function stable,real-time and fast,and the system only needs four multipliers to complete the whole process of bilinear interpolation,which simplifies the algorithm complexity and saves hardware resources compared with traditional methods.The whole system consists of four modules:video image acquisition module,video image cache module,video image interpolation module,video image display module.In this paper,Quartus II 11.1 is used as the development environment,and EP4CE6F17C8,a CYCLONE IV FPGA chip of Altera company,is used as the design platform.The chip has low power consumption,low cost and rich resources.The system uses Verilog HDL to describe each module and realize its functions,including parallel transformation of bilinear interpolation algorithm,mapping the calculation and storage requirements of the algorithm with the available resources inside the FPGA chip,and achieving the advantages of simplified processing,resource saving and speed reaching the standard.In the process of system implementation,functional simulation and verification are carried out on Modelsim platform in the early stage,and system synthesis,layout and wiring as well as board level verification are implemented on FPGA chip in the later stage.Finally,the system realizes the real-time zoom and display of video image from 640*480 resolution ratio to 1024*768 resolution ratio,the field frequency is 60Hz,and the zoom resolution can be reconfigured,the operating frequency of the system reaches 133MHz.