FPGA Design And Implementation Of Video Image Scaling

The purpose of image scaling is to convert the source image signal into the signalwith the resolution we need. Base on the reserch of image scaling algorithm and theanalysis of their advantages and disadvantages, the dissertation chooses a top-downdesign topology to fulfill the design of image scaling and implements its verification inFPGA.The image scaling algorithm is key part. The whole structure is designed startingwith bicubic interpolation，based on the analysis of several interpolation algorithms insubjective visual effect and objective parameter of PSNR. In FPGA implementatin, thedesign seperates the scaling into horizontal scaling and vertical scaling, and uses fourDRAM as data buffer between column row scaling. The advantages of this structureare as follow:column and row scaling can operate with high reliability in dataprocessing independently. It is convenient for the data buffer design with the simplestructure and suitable data size.In addition, the paper presents the design of otherauxiliary module,including scaling parameter calculating and input FIFO module.The design uses verilog HDL to make RTL description to all the modules first,then perform logic simulation with Modelsim and at last, completes the erification withFPGA chips from Xilinx. Through the function simulation and integerated simulation,itis proves that this image scaling design can acheive the desired objectives. Therecoureces are:544registers,1742LUTs,6blockRAM and10Multiplise. Thefrequency of the design is151.MHz. Through the analysis of the performance of theinput images with different resolution,it can be concluded that the design can deal withfull high definition video with the definition of1920×1080,(25frames per second), inreal time.