Design And Implementation Of Video Scaling Based On FPGA

Digital video has some characteristics such as a large amount of data,high requirements to response time.The processing of digital video is a key issue in the field of digital video,if just rely on software algorithm to deal with digital video,the computing power of software and CPU will have a higher demand.While if you make it with hardware,both speed and effect are better than the former,FPGA(field programmable gate array)according to its own characteristics,it is suitable for the video image processing.The content of this paper is mainly aimed at the problem of inconsistency between the video signal resolution of the camera and the resolution of the display during the filming of the film field,at the same time,It can also solve the problem of enlarging the video screen when shooting the video.In the film studio,the camera is usually equipped with a small monitor,the director used a large-size technical monitoring monitor to watch.Due to the different models of the camera,the resolution of the video image is different.So is the display,due to the model is different,the screen resolution is also different.So through taking the FPGA as the design platform to complete the video image processing to meet the needs of video image field.Based on the study of the traditional interpolation algorithm,this paper uses MATLAB to simulate the video image scaling algorithm.After weighing the hardware resources of the chip and the effect of several interpolation algorithms,an interpolation algorithm which can implement the algorithm in hardware description language is selected to design and implement the system.The system can achieve the two functions for the video system conversion and video screen zoom,the design uses modular thinking,the entire system is divided into several modules: color conversion module,cutting and character generation module,I2 C configuration module,DDR3 buffer module,zoom module,video format generation module,and clock module.And the scaling module includes extraction module and coefficient generation module.Use the hardware description language Verilog HDL and dedicated IP check each module to design and implement their respective functions,and through Modelsim simulation of the logic to verify its correctness,and finally layout and routing,Chipscope online logic analysis,timing constraints and board level verification.ISE Design Suite 14.4 is the development environment for the whole system,it takes Xilinx Spartan6 series FPGA chip XC6SLX45 T as the design platform,the chip's characteristics are large capacity,low cost.The final test results is the OSD menu adjustment,you can achieve several video formats between the conversions and two levels of amplification on the video image under any video system,and the display is stable,clear,after the 48 hours of high temperature aging test of the verification,and ultimately there is no abnormal situation,and fully implement the design expectations for camera video monitor.