Design Of Digital Module In 16-Bit Sigma-delta ADC

With the vigorous development of the 5th generation communication technology,the Internet of Things industry is getting more and more attention,and the industry development prospects are getting better.Sensor technology plays a very important role in the entire industry.Sensors broadly connect the real world to the data world,and data converters are the channels between analog and digital signals.Due to various benefits such as reduced power requirements,less space for storing signal data and the ease of data processing in the digital domain,real-world analog signals need to be converted into their equivalent digital form.Therefore,analog-to-digital converters are of great significance in the design of sensor networks.The Sigma-Delta ADC converter based on oversampling and noise shaping technology has become the best choice of ADC because of its efficient architecture and easy implementation.Based on the 0.28?m standard CMOS process,this paper designs and implements a digital module used in a 16-bit Sigma-Delta ADC in a temperature and humidity sensor chip according to the flow of an application-specific integrated circuit.It mainly includes I2 C interface module,register module,logic control module and filter module.The I2 C interface is used to read and write the registers in the register module.The logic control module receives the control bits of the register module and generates the relevant control signals required by the analog ADC module.The filter module receives the sampling clock and sampling data of the ADC and performs down-sampling filtering.The down-sampling filter module uses a three-stage cascade filter structure.The first stage is a cascaded integrator comb filter to complete 128 times downsampling,and the second stage is a half-band filter with a wide transition band to complete 2 times downsampling.The third stage is a half-band filter with a narrow transition band,which completes 2 times downsampling,and the stop-band attenuation of the two-stage halfband filter is 90 dB.The design of each filter is completed using matlab and performed in simulink.The simulation results show that the output precision is over 16 bits.After the modeling is completed,the RTL code is written.For the implementation of the halfband filter,the form of multiplication is converted into a shift and add to reduce hardware overhead.And different from the general implementation of CSD coding,this paper adopts a new shift and add implementation architecture,which effectively reduces the power consumption and area of the half-band filter module.At the same time,the industry-leading UVM verification method is used to build a verification platform to verify the function of the overall filter module,and generate random stimuli for function coverage and code coverage collection.After the design verification of the digital module is completed,the DC tool is used for synthesis,the RTL code is converted into a netlist file,and the layout is performed in the innovus tool to generate a layout file,and the digital layout DRC and LVS inspection are completed by calibre.In this process,the netlist generated after synthesis and the netlist generated by the layout are formally verified with the RTL code respectively to ensure functional consistency.Finally,the timing files generated by the back-end process are used for post-imitation.The simulation results show that the design is correct.