The Design Of Sigma-Delta Analog-to-Digital Converter In Flow Meter SOC Chip

Analog-to-Digital converter (ADC) is one of the most important units in most electronics system. With the techniques of oversamping, noise shaping and digital decimation filtering, Sigma-Delta ADC has many attractive advantages, such as high resolution, insensitive to analog circuit imperfection, power-effective and easy to monolithic integration. So Sigma-Delta ADC is gaining more study and application.This paper focuses on the design of a 16-bit Sigma-Delta ADC used in the flow meter SOC (system on chip). Based on the theory of Sigma-Delta ADC, the design of Sigma-Delta modulator and digital decimation filters are both completed.A 3-rd order single loop modulator is chosen, with an oversampling factor of 128 and a 1-bit quantizer. The sampling rate is 5.632MHz and the signal baseband is 20KHz. Modulator modeling and extensive behavioral simulations are accomplished to obtain necessary related parameters. The circuits of modulator are realized with switch-capacitor circuits in Cadence. To overcome the difficulties induced by high threshold voltage of MOS transistor in Charter0.35um CMOS technology, special circuit architectures,such as two stage class A/AB operational amplifier and current mirror output stage are employed for low-power design. The circuit simulation indicates that the SNR (signal to noise ratio) reached 95dB and the power dissipation of the modulator is only 1.8mW.With multi-rate decimation, the digital decimation filter is cascaded of CIC, amplitude compensation and halfband filters. With the technology of multi-stage decimaton and multi-phase conversion, the improved CIC filter achieves a significant hardware and power dissipation reduction over the conventional approach. Multiplier sharing and pipeline process are adopted to reduce the power consumption and chip area. The filter is implemented with Verilog language, and verified in FPGA.With the simulator of Spectre-Verilog, the mixed-signal circuit simulation of the whole Sigma-Delta ADC is completed in Cadence environment.