The Design Of Low Power Consumption Delta-Sigma Digital To Analog Converter

Digital to analog converter (DAC) can convert a discrete binary signal into an analog signal directly proportional to the value of the binary signal. It is difficult to meet high precision for traditional D/A converter because of the restrictions from analog instruments. Delta-Sigma digital to analog converter (△∑D/A converter) using over sampling technology has the advantage of high precision and high resolution. It is more preponderant than traditional DAC. Its application domain is expanded from traditional audio frequency serving with high precision into high precision measure, telecommunication and so on.The task of this thesis is designing a low power consumption△∑D/A converter used in HART instruments. HART instruments are bus-powered Fieldbus instruments which have critical constrain on power consumption for the components. The power consumption of existing△∑D/A converter is relative high which should be made as low as possible with the precondition that the function of the circuit is met. The parameters are that resolution is 16, over sampling rate is 256, the source is 3 voltage, conversion frequency of input is lower than 10Hz and the current of circuit is no more than 0.45mA.In this thesis, the main principle of△∑D/A converter is analyzed. The implementation of△∑D/A converter is studied.△∑D/A converter has digital part and analog part. The digital part consists of interpolation filter and AS modulator. The analog part includes one-bit DAC and analog low-pass filter. By analyzing every part of△∑D/A converter, it is demonstrated that power consumption is mainly produced by the full-adder and register of digital part. The digital part and one-bit DAC are designed in this thesis. Many implementations of full-adder and register are contrasted and studied. The full-adder and register with the lowest power consumption are chosen. To validate the validity of the function of the circuit, the simulation of behavioral level is done with Hardware Description Language. The simulation and power consumption analyses of the transistor level circuit are accomplished with Hspice. By contrasting the two simulation results, the validity of the function of the circuit is validated. Precise parameter of power consumption is obtained.The layout design adopts TSMC 0.18μm high voltage process. The analog part uses big dimension to reduce the influence of channel-length modulation. DRC and LVS are passed. The area is 110μ×262μm~2.The power consumption is 0.912mW. The average current is 0.304mA. The design target is satisfied with.