Research And Design Of Digital Deci-Mation Filter In Sigma-Delta ADC

With the rapid development of integrated circuits and communications technology,more and more researches focus on Sigma-Delta analog-to-digital converters.The structure of the Sigma-Delta analog-to-digital converter mainly includes two parts:a modulator and a digital decimation filter.The modulator transfers the high-frequency noise in the signal band to the out-of-band through oversampling technology and noise shaping technology.The digital decimation filter is responsible for filtering the quantized digital signal and the corresponding down-sampling work.Since the structure of the digital decimation filter directly affects the area and power consumption of the entire filter,higher requirements are placed on the design of the digital filter part.Based on the study and analysis of the working principle of Sigma-Delta ADC and digital decimation filter,this paper designs a three-stage digital filter structure with 256 times down-sampling according to the requirements of the proposed performance indicators.The first stage uses a CIC filter to achieve 128 times down-sampling work,reducing the operating frequency of the circuit,thereby reducing the workload of the subsequent stage circuit.The cascaded CIC filter structure is optimized,and the four-phase structure is adopted to increase the sampling rate and data processing rate,and reduce the computational workload of the post-stage filter.The second stage adopts a compensation filter structure to compensate for the pass-band attenuation caused by the first stage filter,and optimize the design of the structure to reduce the area consumption of the digital filter.The final stage adopts a parallel half-band filter to complete the further down-sampling operation and the corresponding filtering work.The digital decimation filter of this subject has achieved the performance indicators of input signal frequency of 12.288MHz,output frequency of 48KHz,pass-band ripple of 0.05dB,and stop-band attenuation of 65dB.On the basis of the digital signal generated by the third-order modulator,by modeling the digital decimation filter and designing the half-band filter coefficients and clock divider module,the Simulink-based system of the digital decimation filter designed in this paper is carried out Level simulation and RTL level simulation verification based on Modelsim.Through the spectrum analysis of the simulation results,the feasibility of the digital decimation filter structure designed in this paper is verified,and the 256 times down-sampling work is realized.