The Design And Implementation Of 8-Channel 12-Bit 1MS/s SAR ADC

The analog-to-digital converter(ADC)is the key interface module for converting analog signals into digital signals.In mainstream ADC architectures,the successive approximation analog-to-digital converter(SAR ADC)is widely used in portable electronic devices,wireless sensor networks,industrial control systems,and instrument measuring systems due to its comprehensive advantages such as simple structure,low power consumption,small size,and easy integration.This thesis takes the design and implementation of 8-channel 12-bit 1MS/s SAR ADC as the research subject.It focuses on the in-depth design and analysis of capacitive digital-to-analog converters(DAC),comparator,sampling switch,analog front-end circuit(AFE),and proposes corresponding design solutions.In the design of capacitive DAC,this thesis proposes a hybrid capacitor switching method for the top-plate sampling split capacitive DAC.Based on the hybrid capacitor switching method,an 11-bit split capacitive DAC with "4LSB + 7MSB" is designed.Compared with the traditional bottom-plate sampling,the top-plate sampling can significantly reduce the number of capacitors.Compared with the monotonic or the Vcm-Based capacitor switching method,the proposed hybrid capacitor switching method is not only easy to design the switching logic,but the common-mode voltage of the comparator is almost unchanged.In the comparator design,this thesis uses a cascaded combination comparator with offset calibration,which consists of three stages of Pre-amp and Latch.Not only can it achieve fast comparison of small signal,but it can also meet the design requirements of low noise and low offset.In the design of sampling switch,the bootstrapped switch is used in this thesis.This highly linear sampling switch ensures that no additional harmonic distortion is introduced when the signal is sampled.In the AFE design,this thesis proposes a channel data selection circuit,including single-ended 8 channels or differential 4 channels,and a constant-gm rail-to-rail input and Class-AB output buffer is inserted between the channel data selection circuit and the ADC sampling interface.This can avoid the impact of the AFE on the SAR ADC.Based on 40 nm 1P8 M CMOS process,an 8-channel 12-bit 1MS/s SAR ADC is designed.The chip area is 430 ?m × 300 ?m.The analog and digital modules use 2.5V and 1.1V power supply respectively,and the system clock is 25 MHz.The post simulation results show that the maximum DNL is-0.6/0.5LSB and maximum INL is-0.8/0.6LSB,which meets the static design requirements;When sampling the Nyquist frequency signal,ENOB is 11.3-bit and SFDR is 80.3dB,which meets the dynamic design requirements;Regardless of the power consumption of the buffer,the power consumption of SAR ADC is only 268 ?W,and the FoM is 107 fJ / conv-step.