Research And Design Of 11-bit SAR ADC Based On Reused Terminating Capacitor Switching Procedure

For quite a long time, successive approximation register analog-to-digital converter (SAR ADC) has got extensive applications since it features low power dissipation and small chip area. In recent years, as the continuous shrink of CMOS device feature size and the increase of its speed, an SAR ADC with several tens of MS/s sampling rates and up to 12-bit resolution is achievable, which makes them show a great potential to apply to low power high performance integrated systems such as medical electronics products especially that uses implantable biomedical devices, etc.In this thesis, a low power 11-bit 5-MSamples/s SAR ADC was proposed. It consists of a charge-redistribution DAC, a dynamic comparator, together with asynchronous clock control circuits and registers. The highlight of the work is that based on analysis of the influence of the switching procedure on dynamic power dissipation of capacitive DAC and nonlinearity parameters INL/DNL, a novel switching procedure named Terminating Capacitor Reused procedure was put forward, which results in reducing dynamic power dissipation and chip area. Here the traditional high-frequency clock generator is replaced by asynchronous control logic circuits to reduce design complexity. In addition, by using an external varaiable resistor to adjust the delay time of control signals, the ADC is capable of working in different conversion rates and making full use of the time in transition phase, so as to be tolerant of the comparator speed.The proposed SAR ADC was designed and fabricated in SMIC 0.18-μm mixed signal process. Simulation results show that the SAR ADC achieves an SNDR of 55.1 dB, an SFDR of 68.38 dB and consumes 0.236 mW under a 1Volt supply. The proposed switching procedure is verified by simulation results.