Design Of High Precision 14-bit Successive Approximation Register ADC

With the rapid development of science and technology,the application of digital signal processing(DSP)is becoming more and more widespread.Analog-to-digital converter(ADC)as the medium of the analog and digital worlds,plays a very important role in digital signal processing.Among the many types of ADCs,the successive approximation register(SAR)ADC has the advantages of medium and high accuracy,medium speed,small chip area,and low power consumption,making it widely used in many fields.In addition,the SAR ADC has good compatibility with the CMOS process,and its structure is relatively simple.This allows us to have a large optimization space during design,and reduces design and production costs.This article designs a 14-bit,3MSPS SAR ADC based on XFAB 0.35?m process.Its power supply voltage is 5V,and it has its own reference voltage module.This SAR ADC mainly includes charge calibration digital-to-analog converter(DAC),high-precision and high-speed comparator,calibration DAC,internal reference,reference buffer,and digital control.Aiming at the design requirements of a high-performance SAR ADC that under the premise of improving accuracy and speed,and reducing power consumption and area as much as possible,a three-stage capacitor array DAC with only high-bit sampling is proposed.It not only increases the sampling bandwidth,but also greatly saves the chip area,reduces the mismatch between the capacitors and improves the linearity of the SAR ADC.In addition,the three-segment capacitor array DAC adds redundant bits to make the ADC have over-range capability,that is the analog input voltage deviates from the standard range by 8%,and can still be accurately converted by the added bits.Aiming at the problem that the mismatch of DAC capacitor array capacitance will greatly affect the accuracy of SAR ADC,an improved self-calibration technique is completed to improve the accuracy of ADC.Aiming at the requirements of SAR ADC for the accuracy and speed of the comparator,a multi-stage preamplifier and a latch are cascaded to form a comparator,and the comparator is subjected to offset calibration to achieve high precision and high speed.In order to reduce the pressure of board-level design,high-order compensation technology is used to obtain the ultra-low temperature drift reference voltage,which provides a reference voltage for the DAC module.In addition,providing a reference voltage for the DAC module requires a buffer to drive,and it is implemented using a buffer with a large external capacitor to reduce the complexity of design.This article uses Cadence's Virtuoso software to complete circuit design,simulation verification,and layout design.The simulation conditions are that the SAR ADC conversion rate is 3MSPS,the analog input frequency is 1.06 MHz,and the high capacitor mismatch is 0.1%.The results of pre-simulation show that when the self-calibration technology is not used,the signal-to-noise ratio of the SAR ADC is 65.89 d B and the effective number of bits is only 10.65.After using the self-calibration technology,the signal-to-noise ratio of the SAR ADC is 83 d B and the effective number is 13.49.Position,the effect of self-calibration is better,and better performance is achieved.Then results of post-simulation show that after using the self-calibration technology,the signal-to-noise ratio is 81.38 d B,the effective number of bits reaches 13.22 bits,and the INL and DNL of the segmented static simulation are 1.5LSB and 1LSB,respectively.The designed SAR ADC has high accuracy and speed,and can be used in electronic systems such as sensors,high-speed meters,and wireless communications.