| With the rapid development of wireless sensor technology,biomedical devices and portable devices are widely used.Due to the limitations of battery cost and capacity,low power consumption has become one of the most important design indicators of such devices.As the core component of biomedical equipment,the analog-to-digital converter(ADC)is critical to reduce its power consumption.The successive-approximation register analog-to-digital converter(SAR ADC)is characterized by its simple structure and low power consumption.The field of consumable chip design is highly favored and has been widely researched and applied.This thesis first analyzes the structure and key circuit technology of the low-power SAR ADC.Then derive and analyze five kinds of low-power capacitor switching timing,and simulate power consumption and linearity through Matlab.Finally,a 12-bit 200KS/s asynchronous low-power SAR ADC is designed and completed.This thesis focuses on low-power switching timing.Based on the derivation and analysis of traditional switching timing,monotonic switching timing and Vcm-based switching timing,two new switching timings are proposed.The first is a hybrid energy-saving switching sequence.The structure uses the highest bit splitting technology to split the high bit into a capacitor array that is consistent with the remaining bits,and adopts a two-sided first unilateral switch method.The total capacitor area is reduced by 75%compared to traditional timing.This sequence consumes no energy during the first and third conversions,and saves 97%of energy compared to traditional switching sequences.The second single-ended new energy-saving switch has a simple timing structure and low switching complexity.Compared with the traditional switching sequence,the power consumption is reduced by 96.09%,and the area is reduced by 50%.At the same time,this thesis improves the dynamic pre-amplification stage of the comparator circuit,reduces the circuit power consumption,and reduces the impact of noise on the comparator.Optimize the leakage problem of SAR control logic circuit,improve the accuracy of digital output,and reduce the leakage power consumption of digital logic circuit.The grid voltage bootstrap switch is used to reduce the influence of non-linearity on the system.Derive the redundancy correction algorithm,and design and complete the redundant bit digital error correction circuit.Finally,the overall circuit layout is placed and routed,parasitic parameters are extracted,and the post-circuit simulation is completed.The circuit design and post-simulation of 12-bit 200KS/s asynchronous low-power SAR ADC based on UMC 55nm CMOS process.The simulation is performed under the condition of 0.8V power supply voltage,200KS/s sampling frequency,and input signal frequency of10.9375KHz.Simulation results show that the output SNDR is 67.6d B,the SFDR is 74.4d B,and the ENOB is 10.94 bits.The result of INL is+0.88LSB/-0.65LSB,and the result of DNL is+0.98LSB/-1LSB.Power consumption is 1.6μW.The FOM is 4.1f J/conversion-step,and the overall chip area is 0.113mm~2. |
