Research On Whole Chip ESD Protection Plan Based On 0.18?m CMOS Process

Electrostatic Discharge(Electrostatic Discharge,ESD)is a event of a certain amount of charge transfer between two different potential objects,charge transfer induced discharge,resulting in instantaneous high voltage and high current,in the semiconductor industry will cause the semiconductor chip of the failure,especially when the feature size of semiconductor devices is getting smaller and smaller,ESD-induced failure problems become increasingly serious.In the 0.18?m CMOS process,the ESD design window of 3.3V / 1.8V power supply voltage is very narrow,it will be a challenge for ESD protection,so this paper will be based on 0.18?m CMOS technology for a complete ESD protection research.This paper first introduces the theoretical basis related to ESD protection design,including three commonly used ESD test models and their principles,ESD design window,the characteristics of ideal ESD devices,whole chip ESD protection related concepts,including two commonly used whole chip ESD strategy,ESD protection network based on ESD bus + clamp unit and ESD protection network based on single power rail,and ESD protection strategy between different power domains.It also introduces the theory of ESD test,and focuses on the TLP testing technology in device level test.Then,this paper introduces the ESD basic devices Diode,BJT,MOSFET and SCR(thyristor,silicon controlled rectifier),which is different from other articles,this paper describes the basic principles of ESD devices and how to design these devices in practical engineering by using practical examples,through the analysis of experimental results to verify the theoretical and design expectations,and for the existing problems to improve the method,at the same time,the improved experimental results are presented,the theory combined with practice,not only to deepen the understanding of the theory,but also to master the basic ESD Device design method.Then,the whole chip ESD protection research of 0.18?m CMOS process is comprehensive described in this paper.Firstly,the existing chip is tested and analyzed,and the problems of the chip to be optimized are summarized.Then,three whole chip protection improvement schemes are proposed for these problems,and the ESD devices which will be used are simulated and designed.Finally,the implemented scheme is tested and analyzed,the results show that the scheme can achieve the desired ESD protection.Finally,in order to deepen the research on the ESD protection of the whole chip and improve the ESD design capability of the whole chip,a design and research of whole chip ESD protection under the 3.3V/1.8V mixed power supply voltage also be done,and puts forward the new ESD protection devices LVTSCR and DTSCR,using the newly designed device LVTSCR,DTSCR and Diode to all-round protect the each port of 3.3V/1.8V mixed power supply voltage.With the continuous development and progress of semiconductor technology,the size of semiconductor devices is getting smaller and smaller,and now even to 7nm,but the power supply voltage and ESD protection capability is not equal scaling,so the area of ESD protection unit can not be equal scaled down,to achieve a certain degree of protection must be large enough area.Even use the SCR which has the strongest protection ability in per unit area,the extent of the reduction is not enough.so the future development direction of ESD protection is to meet the protection requirements under the premise of continuous reduce the ESD protection unit area,but according to the current ESD protection methods,devices and levels,to achieve this goal must have a qualitative innovation,which still has a long way to go,predecessors have laid a good foundation for us,we and future generations need continue to strive to explore and innovation.