Full-chip ESD Design On CMOS Process

As an important topic in reliability of chips, ESD(Electrostatics Discharge) has drawn a lot of interest from IC designers and customers. After the process advanced into sub-micro scale, the gate oxide thickness and junction depth shrinked. All these factors lead to more failures of ICs under ESD stress. As a result, various test standards and protection strategies come out.This thesis starts from the test methods, elaborating the existent ESD models. Finally we proved that all these models are reasonable using simulation and mathematical analysis.In this thesis, some common devices used in ESD protection are reviewed: diode,MOSFET and SCR. Their application areas are determined by their characteristics. The forward bias diode provide enough capability to conduct large current flux, while its reverse mode has less leakage current. MOSFET has four terminal and it can be implemented in various application by different combinations. Both surface conduction mode and Bipolar mode of MOSFET can be used in ESD protection. SCR does the best in current conduction, while its high trigger voltage and low holding voltage limited its application. We introduced some method to improve the performance of these devices.Some basic ESD protection circuits are realized by these devices. Generally, the protection circuits can be divided into tow parts: the trigger circuits and the discharge circuits. The trigger circuit can be classified as rise-time-trigger and threshold-trigger.Discharge circuit can composed by simple ESD devices. Various combinations are presented for the sake of diverse features. A case of power clamp is introduced to show how to select trigger circuit and discharge circuit in design.To guarantee discharge path between arbitrary two pins, the ESD network is necessary. In single power domain case, the power rail can be used for discharge bus. In multiple power domain case, connection among each power rail is required. For mixedVoltage I/O, no power rail-based strategies are available but the local protection method.Two-stage protection strategy is introduced to protect the gate oxide. Under pad ESD device design is verified by experiment, which saves a lot of layout space.