ESD Devices And Full Chip Protection Design Based On CMOS Technology

With the rapid development of semiconductor manufacturing processes,process feature sizes shrink from sub-micron to nano-scale,and the gate oxide layer becomes thinner and thinner and the diffusion area becomes shallower and shallower.The development of these processes leads to the reduction of the breakdown voltage of the gate oxide layer of semiconductor devices and the increase of the gate leakage current and then leads the integrated circuit(IC)to be more easily damaged due to Electro-Static Discharge(ESD).Therefore,all electronic products should be incorporated into the chip's reliability design at the beginning of design.For the purpose of full-chip ESD protection,all pads(PAD)must have ESD protection devices.This dissertation focuses on the research of high-performance ESD protection devices and fUll-chip protection designs under CMOS technology.It mainly optimizes the ESD clamp circuit between SCR devices and power supply rails,and the improved device is applied to a full-chip ESD protection network of a data interface chip.The main work of the thesis is divided into two sections:(1)Four new types of ESD protection device was raised on the basis of the test and analysis on conventional ESD protection devices:simple horizontal thyristors,diode-triggered thyristors,low-trigger thyristors,SCRs with embedded LDMOS,and power rail clamp ESD.a.A non-channel LDPMOS-embedded bidirectional thyristor ESD protection device(NonLDPMOS_SCR).The device was tested in a 0.5-μm 5V/18V/24V CDMOS process.The test results show that compared to ordinary LDPMOS_SCR devices,NonLDPMOS_SCR effectively reduces the trigger voltage from 33V to 21.4V and the fail current increases from 3.87A to 4.64A.b.A waffle-type island diode-triggered thyristor electrostatic protection device(IDTWSCR),which was tested in a 0.5-m BCDMOS process.The TLP test results show that it compared to traditional waffle-type WSCR the device effectively reduces the trigger voltage from 18.05V to 14.75V and increases the fault current from 8.13 A to 15.45A,which has a outstanding ESD robustness.The device principle analysis and TCAD 3D simulations explain the effects of the new structure on the electrostatic properties of the device.c.An improved LVTSCR device with a narrow NWell layer added to the NMOS source.The device is tested in a 0.5-μm 5V/18V/24V CDMOS process.The test results show that the device can effectively increase the maintenance voltage from 3.04V to 4.09V compared to the traditional LVTSCR device.The failure current is increased from 2.39A to 5.54A.In addition,the failure current of the modified LVTSCR ten-finger structure is 30A,which can be used in applications requiring ultra-high ESD protection.d.The design of the ESD protection device is clamped between the power rails.This paper optimizes the detection circuit and delay circuit of power clamp devices(PCs),and effectively increases the delay time through MOS tube feedback and reset.The tapeout verification in the 0.18 μm BCD process shows that these improved Power Clamps can achieve human body model protection ratings of 10kV and above.(2)For the ESD protection requirements of a data bus interface chip,determine the ESD design window for each port,and select the ESD protection device for I/O pins,power rails,and bus pins.Especially for the signal transmission requirements of the bus port-7V-12V,a bidirectional SCR device with high retention voltage and high failure current embedded in a LDPMOS without channel is designed.Finally,a full-chip ESD protection network is formed and the layout layout is optimized.