Research On ESD Protection Device Based On 0.18?m BCD Process

Electrostatic discharge(ESD)is a discharge phenomenon in which charge transfer occurs when objects carrying electrostatic charges are in contact with each other,which can produce transient high voltage and large current.As the size of semiconductor features becomes smaller and the scale of integrated circuits continues to expand,the immunity of semiconductor devices to ESD events has gradually weakened,and chip failure and yield reduction caused by ESD have received more and more attention.In this case,the ESD protection network design of integrated circuits has become an indispensable link in the chip development process.This thesis mainly focus on the research of full-chip ESD protection scheme.Firstly,introduce the theoretical knowledge in the field of ESD protection,including the calculation method of the ESD design window,the working principle of the basic ESD device,and the design strategy of the full-chip ESD protection network,etc.Then based on the 0.18?m BCD process,the ESD protection design of the integrated circuit is introduced in detail.It mainly involves the design of the ESD protection device and the design of the full chip ESD protection scheme.In the design of ESD protection devices,this thesis mainly studies various methods to reduce the trigger voltage of GGNMOS,including increasing the ESD layer and using gate resistance.It also uses GGNMOS and PMLSCR to design a stacking device suitable for high-voltage circuits,to verify the trigger voltage and the holding voltage of the stacking device can increased linearly as the number of stacked cells increases.These can solve the problem that traditional ESD devices in the field of high-voltage protection,such as low holding voltage and prone to latch-up problems.For ESD protection of highvoltage bidirectional ports,back-to-back devices are designed using LDNMOS provided by the process,and a bidirectional device based on embedded SCR LDNMOS(LDNMOS_SCR)structure was proposed.By widening the device size and dividing the device emitter,the device's holding voltage is increased,and the trigger voltage reduced by increasing the gate resistance.The device has snapback characteristics in both directions,and can perform ESD protection on ports that have both positive and negative voltage inputs.In the full-chip ESD protection design section.For the protection design of multiple-supply circuit,starting from analyzing the PCM parameters of the 0.18?m BCD process,the ESD design window between each port is calculated and designes a special ESD protection scheme.Finally,the ESD devices that meet the requirements is connected to the circuit,and the full-chip design solution is taped out and tested to verify whether the solution can meet the 8KV design requirements.Perform failure analysis and improvement on the ports that fail the test,and finally get a reliable full-chip ESD protection scheme.