Design Of Low Power Successive Approximation Analog-to-digital Converter Based On 802.11n WLAN Application

With the popularization of wireless local area networks and the development of the Internet of Things,the low-cost and low-power WIFI chips have broad market prospects.As a part of the WIFI receiver,the analog-to-digital converter is responsible for the signal conversion from the analog front-end to the digital baseband.And it is of great significance to reduce the power consumption of the analog-to-digital converter.This paper first introduces the principles and specifications of analogto-digital converters,and it also summarizes the advantages and disadvantages of various mainstream analog-to-digital converter architectures.It is concluded that the successive approximation converter architecture can better meet the high-precision high-speed and low power requirements in WIFI application.This paper also introduces,analyzes and summarizes related technologies about the high-speed and low-power successive approximation analog-to-digital converters,including lowpower capacitive DAC switching scheme,redundancy method,high-speed low-power comparator and asynchronous SAR logic.Then based on the target specifications,this paper determines the toplevel architecture and the specifications of core modules,and it also shows the detailed circuits and simulation results including bootstrapped switch,comparator,asynchronous SAR logic and digital error correction logic.For the reference voltage buffer,the driving requirement is released by systematic optimization based on RC settling model.And a flipped-voltage follower reference voltage buffer is proposed to further reduce the system power consumption.Finally,the system layout and post-simulation result are given.Based on TSMC 40 nm 1P6M process,this design achieves a highspeed low-power SAR ADC.With an input signal at 21.25 MHz and 1.4Vpp,the simulated SNDR and SFDR is 58.2dB and 72.4dB,respectively.The power consumption of only ADC core part is 1.42 mW and the system power consumption with reference voltage buffer is 2.03 mW.The FoM value is 13.3 fJ/conversion-step for the ADC core alone and is 19.0 fJ/conversionstep for the ADC with reference voltage buffer,respectively.