Research And Design Of Single Channel 8-bit High Speed ADC

With the continuous development of science and technology,analog-to digital converter(ADC)have became the core components of almost all electronic devices.ADCs have a wide range of applications and requires different sampling rates and resolutions for different applications,including ultra-bandwidth systems,radar detection,optical communication links,digital receivers,and Fast Ethernet.Among them,high-speed medium-resolution ADC is a key component of ultra-bandwidth system,disk drive readout channel and optical communication.However,the shrinking size of the semiconductor process makes the study of highspeed ADC a challenge.The application of high-speed ADC is the first choice for full parallel structure ADC,but the full parallel structure reduces the speed of ADC because the number of comparators leads to high input impedance,so it is difficult to use high speed 8-bit resolution applications.In order to overcome the speed limitation of input impedance,a two-step ADC is realized in this dissertation.The structure has a two-level flash ADC,which realizes equivalent pipeline operation under the action of clock control,thus obtaining high digital output and low digital output.In this dissertation,three main modules of two-step ADC are studied and introduced respectively.The bootstrap switch is used to improve the linearity of the input signal and reduce the influence of the non-ideal factors of the switch on the performance of the system.The dynamic comparator is used to reduce the power consumption of the circuit and shrink the delay of the comparator.The correlative correction circuit is designed to reduce the offset of the compactor and improve the performance of the system.In addition,the circuit also uses the interpolation structure,further cuts down the number of comparators,decreases the input impedance,and finally uses redundant correction circuit to export 8-bit of digital code.There is also no amplifier in the structure,thus reducing the power consumption of the circuit.Based on the 40 nm CMOS process,the key module and the whole circuit in the two-step ADC are simulated after the layout of the Cadence simulation software.Finally,the core area of the map is 390?m?190?m.The results of the post simulation are: When the input frequency is about 100 MHz,the sampling frequency is 1GHz,the signal-to-noise distortion ratio reaches 43.8172 dB,spurious free dynamic range is 54.7353 dB,the effective number of bits is 6.9862 bit.The total power consumption of the circuit is 16.3mW,which basically meets the requirements of the design.