An Ultra High-speed Comparator In 0.18μm CMOS

As the link of analog signal and digital signal, the Analog-to-digital (A/D) converter is one of the most crucial components in the telecommunication, radar, sonar and many consummative electronic products. With the access speed of data storage channel increasing dramatically, the design of ultra high-speed A/D converters becomes increasingly important. As far as the ultra high-speed A/D converter with medium resolution, the full Flash A/D structure is deemed as almost the only ideal choice. The comparator is an indispensible part for all A/D converters, especially for full Flash A/D converter. Its speed, power and noise have great impact on the characteristic of the whole A/D converter.Generally, the latched comparator structure is adopted in ultra high-speed application to satisfy the requirement for speed. Nevertheless, the ordinary CMOS latched comparator exhibits large offset voltage, greatly influencing the resolution of the comparator and thus restraining its application in high speed A/D comparator with high resolution. Therefore, the preamplifier regenerative latched comparator is used presently for ultra high-speed comparator.Based on preamplifier-latch theory, an ultra high-speed CMOS comparator, which is applied to ultra high-speed Flash A/D converter, is proposed in this paper. The presented comparator is composed of a preamplifier which includes a positive and negative resistance connected in parallel as its load, a regenerative latch whose key components are inverters connected end to end, and a simple output stage which is made up of two cross-coupled NMOS transistor and the PMOS common source amplifier. When clock is low, the regenerative latch is disabled and the difference between the input and reference is amplified by the front-end amplifier. When clock goes high, the amplifier is disabled and the latch begins to amplify the difference established at its input to generate logic levels at the output.Based on SMIC 0.18um/1.8V mixed-signal CMOS process, the comparator was designed and simulated by Cadence Spectre. Simulation results show that the circuit can work under as high a clock frequency as 1.25GHz. The maxim offset voltage is 0.6mV. Thus, with 1.0V input swing, the circuit can be used to realize 10-bit resolution.