Research On High Speed Low Power SAR ADC

With the fast development of the wireless communication systems and the portable test instruments,the requirements for speed and power consumption of analog to digital converters?ADCs?are becoming more and more stringent.Successive approximation register?SAR?ADC has inherent simple architecture,small area,low power consumption and can adapt to the scaling of the size of CMOS devices.It not only occupies a vast market in low-speed and low-power applications,but also gradually emerges in the field of high-speed and low-power consumption.Therefore,it is of great significance to study high speed low power ADC based SAR.The SAR ADC with single IP core is studied in detail.This project aims to improve the conversion speed of SAR ADC as much as possible while maitaning low power consumption.This paper investigates the current research situation of SAR ADC both at home and abroad,evaluates several common structures of SAR ADC and analyzes the non-ideal factors in the design of SAR ADC.Eventually,the design scheme suitable for this project is determined.The designed SAR ADC includes sampling switches,DAC capacitor arrays,comparators,offset correction modules and SAR control logic circuits.Bootstrapped switch with high linearity is adopted to improve accuracy.Improved segmented capacitive structure is used,of which the the highest bit of the lower part is removed,thus effectively controlling the area and power consumption.Partial-monotonic switching scheme is proposed which consumes 50%less power than monotonic timing schemes and 25%less than V_cm-based switching schemes.Double-tail comparator is used to lower the static power consumption and an offset calibration circuit based capacitor compensation is proposed.The Monte Carlo simulation results show that the offset voltage is 5.14mV before calibration and 0.37mV after calibration.The SAR control logic directly reflects the output of the DAC to the switch control terminal,thus reducing the delay of the critical path and improving the speed of ADC.A high speed low power SAR ADC is designed in this paper using 40nm CMOS process.The measurement results show that the speed of ADC is up to 200MS/s,SNDR is 50.1dB,SFDR is 65.1dB and the power is 9.2mW.