Research And Design Of Comparator Applied To High Resolution And Low Power SAR Adc

Data converter is the bridge between analog circuit and digital circuit and widely used in electronic equipment and communication device,such as base station,mobile phone and WiFi,etc,.Recently years,the wearable device and Internet of Things(IoT)become very popular and there is a great demand for high resolution and low power analog-to digital converter(ADC),especially for battery-powered device,which is very sensitive to power.Comparator is the key module of an ADC and dissipates much power which has a great impact on performance of ADC.The definitions of data converter performance metrics would be given at first in this dissertation and then the most popular architectures of ADC,including their characteristics and application.A summary of trend of ADC is followed based on recently years published papers.Comparator is discussed in detail subsequently,including its requirement and difficulties.The classical architectures of comparator and those corresponding characteristics and application are also discussed.Based on the research of comparator and having an insight of offset and noise,this thesis designs a comparator applied to 16 bit 1MS/s low power SAR ADC whose LSB is as low as 55 uV.The comparator consists of pre-amplifier and latch.Because the comparator has to compare signal less than half LSB about 27 uV,multi-stages amplifiers are used to get a large gain.In addition,the comparator must do offset cancellation to obtain small offset voltage.What's more,once the ADC becomes high resolution,the noise of comparator will be more important.So as to avoid decreasing performance of ADC,the noise of comparator should be less.Once everypart of the comparator is optimized,a power-down circuit is added to reduce power which would disable the comparator and turn off static current dissipated by pre-amplifiers when all bits are decided.The comparator is design in TSMC 0.18 um process and its supply voltage is 1.8V.According to the post layout simulation result,the stand distortion of offset is 3uV and equivalent input noise is 16.3uV.The power is 3.8mW(2.1mA)when is clock of comparator is 36 MHz.The performance of comparator satisfies the requirement of 16 bit 1MS/s SAR ADC.