Research And Design Of A High-speed And High-precision Successive Approximation ADC

With the appearance of the Internet of Things epoch,for example,autopilot area and intelligent vision area have gradually developed.CMOS image sensor is an important pair of "eyes" in these fields.How to increase the frames per second and resolving ratio of CMOS image sensor has become a hot spot in the scholastic and industrial groups.The analog-to-digital converter(ADC)is an important composition in the CMOS image sensor,and its speed and precision immediately decide the capability of the CMOS image sensor.As the integrated circuit process craft becomes more and more advanced,the successive approximation ADC(SAR ADC)is compared with the pipeline ADC(Pipelined ADC)and Sigma-Delta ADC.It does not require complex design,consumes less power,and the chip layout area is small,and the successive approximation ADC has moderate high accuracy and moderate velocity.On the whole,the successive approximation ADC is more appropriate for the current CIS research and design.Based on the application background of CMOS image sensor,this thesis uses HLMC 55 nm process technology to study a successive approximation ADC,its accuracy is 12 bits,and the speed is 120KS/s.This thesis studies the common structure of successive approximation ADCs.Its core module circuit includes three portions.This thesis has devised three main circuit modules.In the creation of the DAC circuit,the merits and defects of the segmented capacitor type successive approximation ADC are analyzed.The differential two-step structure DAC capacitor arrange is confirmed,and the capacitor arrange is separated into a high 6-bit group and a low 6-bit group.According to the upper and lower positions,the two sides are linked to the two ends of the voltage comparator,one positive phase port and one negative phase port.Aiming at the sampling disjunctor,this article uses the gate voltage bootstrap circuit structure,it validly reduce the sampling error.For the overall SAR ADC system,the design of the DAC decreases the space and energy expansion of the microchip.When designing the comparator,a new structure of the regenerative comparator is used,which saves the energy consumed in the comparison process and increases the comparison rate.When designing the SAR logic control circuit,researched many types of flip-flops,and finally adopted a new type of logic unit.Only the capacitance of the high 6-bit group participates in the sampling of the input signal,and the capacitance of the low 6-bit group does not participate,which validly decreases the circuit energy dissipation and ameliorates the working rate of the circuit.After the main circuit modules are designed,the whole successive approximation SAR ADC is simulated.The DNL of the tested ADC is-0.3/0.3LSB,and the INL is-0.3/0.42 LSB,which has good static performance.The whole successive approximation ADC adopts dual power supply,the digital part is 1.5V,the analog part is 3.3V,and the system clock rate is 2MHz.The previous emulation result reveals that when the import sine wave range is 1.65 V,the rate is 585.94 Hz,and the sampling rate is 120 KHz,the ENOB is 11.78 bits,which has good dynamic performance.