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A Readout Circuit For Differential Capacitive Sensor

Posted on:2021-02-09Degree:MasterType:Thesis
Country:ChinaCandidate:Y X PanFull Text:PDF
GTID:2428330620464125Subject:Engineering
Abstract/Summary:PDF Full Text Request
With the development of Micro-Electro-Mechanical System(MEMS)inertial technology,MEMS inertial devices are widely applied in both military and civilian fields.They have the advantage of small size,low power consumption,excellent stability.A differential capacitive sensor is widely used to detect physical quantities such as linear displacement and acceleration.It can be represented by two capacitors whose capacitances change with physical quantities.As the variation of capacitance is very weak,the implement of the readout circuit is a challenge to IC engineer and this field has become a key research in institutes and corporations.With focus on the theoretical research and circuit design in readout circuit for differential capacitive sensor including the model of system,noises and so on,there different structure of interface circuits are compared including CTV,CTC and SC.And the type of switched-capacitor(SC)front-end detection circuit is designed.In this thesis,a fully differential gain-boosted op-amp is designed in capacitance-tovoltage converter and sampling holder.A new structure is proposed and its function is improving the linearity.To reduce the flicker noise and DC offset,the correlated double sampling(CDS)technique is proved reliable.Every MOS switch and phase of clock timming is punctiliously determined in consideration of non-ideal factor.At the end of readout is a low-pass filter with a chopping op-amp.A clock generatior,bandgap voltage generatior,current reference generatior,divider as well as timming generatior are also realized.The distinctive advantages of this readout circuit system are noise suppression,good linearity and adaptability,for which it is adapt to different kinds of capacitive sensor by adjusting different parts of on-chip programmable capacitors array(PCA).The readout circuit is simulated and fabricated in 0.18 ?m CMOS technology.The layout of readout circuit is prensented.The simulation results indicate that the-3dB bandwidth is 25 kHz and output noise is about 3.64?V/? at 100 Hz.The circuit can apply to 10~100pF of each static capacitance and up to 8 times programmable gain.Finally,the capacitance-to-voltage transfer characteristic curve is presented.
Keywords/Search Tags:Readout Circuit, Gain-Boosted Op-amp, Capacitance-to-voltage Converter, Linearity, Correlated Double Sampling
PDF Full Text Request
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