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Noise Analysis And Design Of CMOS Image Sensor Readout Circuit

Posted on:2022-10-01Degree:MasterType:Thesis
Country:ChinaCandidate:Z C CuiFull Text:PDF
GTID:2518306605469464Subject:Master of Engineering
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CMOS image sensor are widely used in automotive electronics,security,consumer electronics and other fields.This paper designs a CMOS image sensor readout circuit based on the research of image sensor noise mechanism,and analyzes the noise of the readout circuit.The main work of the thesis is as follows:Firstly,the noise of the pixel is analyzed.In order to reduce the power consumption of the pixel and improve the dynamic range,a new structure of 6-tube pixel is proposed.The dynamic range is improved by connecting the extended capacitance Cext.The current source in the 4-tube pixel is replaced by the dynamic tube,which can reduce the power consumption.The power consumption of the 6-tube pixel is only 7.71n W,and the dynamic range is 76.9dB.The noise model of the 6-tube pixel is established,and the simulation shows that the noise of the 6-tube pixel is 47?V.In order to reduce the fixed pattern noise of the pixel,a correlated double sampling circuit is designed to sample the reset signal of the pixel and the electrical signal after the photo-generated charge is transferred,and subtract the signal obtained from the two samples to eliminate the fixed pattern noise.In order to reduce signal distortion,a bootstrapped switch is used to replace the MOS switch.A two-stage programmable gain amplifier with switched capacitor structure is designed to adjust the range of photoelectric signal.The optional amplification multiples are 1,3,5,9,15,25.The setup time of the programmable gain amplifier is about 6?s and the output noise is 70.3?V.To make the CPU and memory easier to process signals,a column level SSADC with 8 bit precision and 10 KS/s sampling rate is designed to meet the requirement of 30fps.SSADC consists of counter,slope generator,comparator,lock register and other modules.The slope generator uses 8-bit current-steering DAC structure,which including register,decoder,latch,current source array,reference current source generation circuit.The clock in this comparator is 20MHz,and the accuracy is less than 100n V.The average offset voltage is about 222?V,and the kickback noise is less than 34?V.The simulation results show that the ENOB of SSADC is 7.14 bit,SFDR is 49.8 dB,SNR is 44.7 dB.In this article,the readout circuit of the CMOS image sensor is designed in CMOS 0.18?m technology.The simulation results show that the resolution of the CMOS image sensor is128×128 pixels,and the maximum power consumption of the pixel array is 126?W;By adjusting the working mode of the pixel and the amplification factor of the programmable gain amplifier,the readout circuit can correctly process the photoelectric signal in the range of 1p A?7n A,and the dynamic range reaches 76.9dB.
Keywords/Search Tags:pixel, noise, correlated double sampling, programmable gain amplifier, analog-to-digital converter
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