Research And Design Of Readout Circuit For Single-Photon Lidar Array Detector

Single photon avalanche diode(SPAD)has been applied in 3D lidar imaging detector due to its advantages of high gain,high sensitivity and high detection efficiency,and the anti noise performance and signal processing ability of array readout circuit often directly affect the imaging quality.With the development of detection array towards high density,high speed and long distance,higher requirements are put forward for its array readout circuit.According to the development trend of lidar array detector,the detection range,detection accuracy,imaging quality and readout speed are studied in this thesis,the main research contents are as follows:(1)A pixel structure of large FSR and high precision is studied.In order to achieve a long detection distance and a high detection resolution at the same time,the time of flight of photons is measured by combining TAC and counter in the pixel unit.The counter is used as the coarse timing and the TAC is used as fine timing respectively in the process of detection,which solves the contradiction of dection distance and resolution.The simulation results show that the pixel can achieve a detection distance of 300 m and a temporal resolution of less than 50 ps.(2)The noise reduction and quantization readout are implemented for analog signal readout.Firstly,in order to improve the image quality,a two-stage correlated double sampling(CDS)circuit is used to eliminate the noise from the pixel unit and column level respectively.The CDS circuit has simple structure,which is suitable for large-scale array.Secondly,a 9-bit successive approximation(SAR)ADC circuit is designed to quantize the analog signal.The SAR ADC uses the bottom plate sampling method and pseudo differential structure to achieve the tradeoff between accuracy and power consumption.The simulation results show that the DNL of the CDs circuit is less than 0.2 LSB and its INL is less than 1 LSB.Moreover,the voltage variation is only 2 m V at 0?40?,which demonstates the good linearity and temperature characteristics.Based on SMIC 0.18 ? m standard CMOS process,the CDS circuit and SAR ADC circuit are taped out and verified.The test results show that the linearity of the CDS circuit can reach 99.9%,and the results are basically consistent with the post simulation.In addition,the SNDR of the designed 9 bit SAR ADC circuit is 49.97 d B,and its ENOB can reach 8.01 bits.(3)A high-speed readout mode is designed for array readout.The readout signal consists of digital signal and analog signal.For digital signal,in order to reduce the number of output pads,the digital parallel signal is converted to serial signal.The parallel to serial converter circuit is driven by two-stage half rate clock,which can reduce the working frequency and improve the readout speed.The simulation results exhibits that when the clock driving rate is 20 MHz,the readout speed can reach 40 MHz.In addition,it is very difficult to achieve high-speed readout according to the traditional readout method of pixel by pixel.This paper adopts 8-channel multiplexing and 4-channel parallel output mode for 32 × 32 detection array,which can greatly improve the readout speed and thus improve the frame frequency.Moreover,when the readout is multiplexed,the CDS circuit and ADC circuit corresponding to the analog readout part can also be multiplexed,thus reducing the detector area.The simulation results show that the frame frequency of the designed array is greater than 15 kfps and the overall chip area is about 4 mm^2 by using the readout mode of multiplexing and parallel output.