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Design Of A High-figure-of-merit Readout Circuit For CMOS Image Sensor

Posted on:2012-09-22Degree:MasterType:Thesis
Country:ChinaCandidate:X L LiuFull Text:PDF
GTID:2218330362456435Subject:Pattern Recognition and Intelligent Systems
Abstract/Summary:PDF Full Text Request
The main advantages of CMOS image sensors are their high level of integration, random accessibility, and low-power operation. In recent years, vision systems based on CMOS image sensors have acquired significant ground over those based on charge-coupled devices (CCD). Nowadays, CIS'dynamic range (DR) is become higher and higher. Besides, with the expanding array of pixel, improvement of reading speed, readout circuit design becomes a bottleneck. Therefore, designing a high high-figure-of-merit (FOM) readout circuit is real challenge.In this paper, the speed, noise, accuracy of readout circuit is thorough studied. And a high-figure-of-merit readout circuit for 1M(1024x1024)CIS is designed. Readout circuit include three essentoal blocks: the correlated double sampling (CDS), programmable gain amplifier (PGA) and the interface circuit. This readout circuit is implemented in TSMC 0.18μm 3.3V mixed-signal CMOS process. The post simulation shows the readout circuit allows the frame rate of the 1M CIS to 20fps (frames / sec), and dynamic range attains 70 dB.This work focuses on the design of CDS and PGA. Traditional CDS employs two column-amplifiers, which can easily lead to the column fixed pattern noise (FPN), more power consumption and area. However in our CDS circuit, each column requires only one column-amplifier, the column FPN noise can effectively reduced, both power consumption and area decrease by half as well. We propose a new PGA structure, which makes a capacitance matching and layout relatively simple, large feedback coefficient, low noise, high linearity. We propose an Operational Transconductance Amplifier with a variable compensation capacitor for regulating its bandwidth. In this way the power of PGA is greatly reduced.The Nanosim simulation shows: CDS'power is only 1mW; PGA attains the 0~18dB dynamic range in steps of 6dB with 12-bit accuracy, and power consumption is only 10mW; interface circuit consumes 4mW at 25Msps. The figure-of-merit (FOM) of readout circuit is 30 dB gM Hz /mW.
Keywords/Search Tags:CMOS image sensor, Readout circuit, Correlated double sampling, Programmable gain amplifier
PDF Full Text Request
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