Research On The Key Technology Of Line Scan For Readout Circuit Of CMOS Image Sensor

For the CMOS image sensor which can be applied to the satellite geological disaster monitoring system,we must consider the fact that the monitoring system is moving fast relative to the ground,resulting in the short exposure time of the image sensor.If the traditional array of staring imaging is adopted,the image will appear blurred,leading to poor imaging quality,so we should use a new imaging approach.At present,the industry usually use the line scan image sensor of time delay integration(TDI),which accumulate these signals through the multiple exposure of target scene.It is equivalent to increase the exposure time,thereby enhancing the signal to noise ratio of image.In this paper,we focus on the research of TDI type readout circuit of CMOS image sensor.The synchronous accumulation timing and the improvement of the effective accumulation series is focused on carefully.Firstly,the basic modules of the readout circuit are analyzed and simulated and the 3 transistor pixel structure with the pinned photodiode is determined as the base of the following simulation.Then,in order to ensure the output signal range is large enough,the rail to rail output buffer is adopted,which has the input range of 1.5V~4V.When a square wave of 2MHz input,this circuit can driving the 20 pF capacitive load with an offset voltage less than 1mV.Secondly,some kinds of correlated double sampling(CDS)circuits are analyzed,and a modified double end output structure has the function of offset voltage elimination which is used in the following chapters.Finally,the analog domain accumulator with TDI function is focused on,and the structure can be proved rational through a large number of formulas,and the synchronous accumulation of TDI is verified by simulation.Then the parasitic parameter modeling is presented for the problem of effective accumulated series and thus the original structure is modified and proved feasible by the formulas.The simulation results also show that the modified structure can improve the effective accumulation series of the analog domain accumulator.The simulation in this work is based on CSMC 0.5?m technology.A TDI array of 100 is adopted in this work in order to explain and verify the rationality of the structure.In simulation,the transition time also named as integrated time is 90?s and the simulation shows that the accumulator linearity is 97%.