Research And Design Of Sample-and-hold Circuit For Image Sensing Readout

With the rapid development of mobile electronic devices,the requirement of mobile phones,cameras and other imaging for photos and videos are getting higher and higher,which are benefited from the rapid development of CMOS technology and image sensing technology.CMOS image sensing mainly includes sensor arrays and sensing readout circuits.The size of CMOS image sensor pixels is shrinking,but the sensor noise is still being optimized,the sensitivity is enhanced continuously,and the sensor can collect more photon signals effectively.Correspondingly,the market demand for sensing readout circuits is getting higher and higher,and this paper is proposed in this context.This paper compares the development history of traditional CCD circuits and CMOS image sensing circuits firstly,and analyzes their advantages and disadvantages.The CMOS image readout circuit has gradually become the mainstream of the market with low power consumption,low cost,high integration and excellent performance.In this paper,the two most common CMOS image sensor models and bias circuits are analyzed in detail.On the basis of comparing the advantages and disadvantages of different sensing readout circuits,an integral amplifier circuit suitable for diode sensors is selected.A readout circuit combining integral circuit and correlated double sampling is proposed to reduce the reset noise and fixed mode noise of the CMOS image sensor effectively.In order to improve the linearity of the correlated double sampling circuit,a gate-voltage bootstrap switch with a body modulation and a lower-plate sampling technique are employed.Based on the traditional image sensor,this paper designs a correlated double sampling circuit for the op amp offset voltage compensation,which can eliminate the correlated 1/f noise,reset noise and low frequency noise in the pixel readout period.With the GSMC 0.13?m standard CMOS process,the CTIA readout circuit designed in this paper can adapt to the illumination of different radiation intensity.By using the fourth and fifth layers of metal as MIM capacitor plates,this circuit achieves 1 to 8 times magnification adjustment,and an amplification range of 200pA to 15nA input integrated current.The readout circuit power supply voltage is 3.3V,input signal range is 0.7V~2.1V,the swing is 1.4V,the charge storage capacity is 3.5×10~6,and the linearity of the readout circuit is 99.99%.The readout circuit is suitable for an array size of 640×480 VGA resolution,and the output signal frame rate is 60 Hz.The design has completed the unity gain sampling using the lower plate sampling technique,which can compensate the circuit offset voltage effectively.In the post-simulation,the worst-case linearity is 100.15dB,and the output signal has 14-bit precision under all the processes corners.The correlated double sampling circuit can complete the compensation under the condition that the operational amplifier offset voltage is±5.3mV,which reduces the deviation requirement of the readout circuit.