Research And Design On High-speed Time-interleaved Analog-to-digital Converter

With the critical dimension scaling down according to the Moore’s law, the speed of digital signal processing is highly improved. Analog-to-digital converter(ADC) works as the bridge between analog signal and digital signal. Its performance to be higher precision and higher speed is desired by the whole system. Under the sampling frequency of intermediate frequency(IF) and radio frequency(RF), high-speed ADC is widely used in wideband communication, instrument, measurement, radar, software radio and so on. It has high military and civil value. The conventional high-speed ADC architectures with single core are studied by researchers at home-and-broad for years. Its fundamental theory and realization method are highly mature. The converting speed and resolution are close to the limitation and it is hard to further improve with the improvement of process.Time-interleaved architecture utilizes the clock distribution technique to control several ADCs working one-by-one, and thus realize the multiplication of the ADC converting rate. This architecture is one of the most efficient ways to realize the ultra-high-speed ADC. Theoretically, the available converting rate is unlimited. However, because of the device mismatch, temperature misdistribution and stress misdistribution in chip, the mismatches among channels will influence and limit the performance of the time-interleaved ADC(TIADC). The mismatches contains offset mismatch, gain mismatch, timing mismatch, bandwidth mismatch and so on. What’s more, both the precision of the high-speed clock and the stability of the multi-phase clock will affect the TIADC’s performance either. In this paper, the above problems are deeply studied. The main work and innovation are listed below:1. Analysis and calibration for the mismatches among channels: The mismatch model is firstly built based on the analysis of the mismatches and the influence on the ADC’s performance is demonstrated by MATLAB. Among the mismatches, offset and gain mismatches are calibrated by the equalization technique in foreground and background. For the timing mismatch, a global sampling technique is firstly proposed and expected to eliminate the timing mismatch entirely. Then, an adaptive background calibration method based on the digital output difference value between adjacent channels is introduced. It is a combination of digital filed and analog filed, and thus reduces the hardware cost in digital calibration method and also the complication in the analog circuit. It provides an advanced solution to mitigate the timing mismatch. And on this basis, an improved calibration by the derivative of the digital output is proposed to enlarge the applicable frequency range. This method utilizes the derivative of the digital output to estimate the timing mismatch and is with much higher precision. It is effective to detect and calibrate the timing mismatch in the entire Nyquist range.2. Design and realization of the high-speed and low-jitter clock generator: A gate leakage model is proposed for the low-voltage and thin-gate MOSFET in nano-meter process. To mitigate its contribution on the charge-pump phase-locked loop(PLL), a voltage-to-voltage circuit is introduced. And on this basis, a clock generator with output frequency of 1.62 GHz is designed. With the optimization of loop stability and loop noise, the jitter performance of the output clock is 2.27 ps.3. Design and realization of the multi-phase clock generator: A four-phase clock generator is designed based on the delay-locked loop(DLL). It works at a frequency of 400 MHz with a duty cycle of 50%. To solve the phase mismatch among clocks, an adaptive background calibration technique is proposed. It utilizes the charge pump and filter capacitor to detect the phase mismatch and realize the calibration by regulating the analog delay buffer. The design is realized under 65 nm standard CMOS process. The test results show that the DLL is locked and output the multi-phase clock correctly. After the calibration, the delay time is reduced from 690 ps to 630 ps which is close the standard value of 625 ps.4. Design and realization of the two-channel TIADC: For a 12-bit 800 MSPS ADC, a two-channel time-interleaved architecture is adopted based on the power analysis in pipelined ADC. The stage resolution is 2.5 bits. When designing the high-performance amplifier, thin-gate MOSFETs are widely used to enlarge the output swing and bandwidth. Bandgap reference, low-voltage-differential signaling(LVDS), mismatch calibration circuits are integrated. The design is realized under 65 nm CMOS technique with a core area of 5×3 mm2. The test results show that the proposed calibration techniques are effective to reduce the mismatches. The dynamic performances of the TIADC are: SFDR is 58.9 dB,SNDR is 49.5 dB and ENOB is 7.9 bits.