Design Of Low Power Charge Pump Phase Locked Loop

With the rapid development of integrated circuit industry,the characteristic size of integrated circuit process is getting smaller and smaller.7nm and 5nm processes have been realized in mass production,and 3nm is also in the plan.Market demand for integrated circuit chips tends to high speed,high integration,low power consumption and low cost.As a precise on-chip clock source,the PLL can be widely used in all kinds of mainstream chips.Among them,the Charge Pump Phase Locked Loop(CPPLL)has the advantages of large capture range,programmable,small Phase error during locking,and high resolution,making it a hot research type of PLL.The research direction of this paper is the design of low power charge pump phase-locked loop.Its core submodules include a Phase Frequency Detector(PFD),Charge Pump(CP),Loop Filter(LF),Voltage Controlled Oscillator(VCO),and Divider(DIV).Based on the basic principle of each module,the continuous time linear model and noise model of the system are given.According to the requirement of the index,the structure of the sub-circuit is selected,the non-ideal effect in the circuit is analyzed,and the direction of the structure optimization is given.Based on the second-order low-pass filter,the stability and phase noise of the MATLB simulation system are used to assist the loop design.Finally,the design of the whole CPPLL core circuit and system is completed,and the layout drawing and post-simulation are completed.The working voltage range of this design is 1.08?1.32 V,taking into account the TT,SS,FF process corner and wide temperature range(-40?125?)design,under the condition of process corner and temperature combination,CP charge and discharge current mismatch is less than1%.The VCO uses a complementary cross-coupled LC oscillator,which oscillates at a central frequency of 2.4 GHz,and its phase noise is-123.8d Bc /Hz@1MHz.The working current of the PLL system is 1.78 m A when locked.