Charge-Compensation Technique For Reference Voltage Of High-Speed ADC IP

Rapid development of System-On-Chip has requirements on Analog-to-Digital Convertor performance and power-efficent. As a quantization standard of ADC, the precision, stability and noise performance of reference voltage effect ADC performance directly. Charge is released or absorbed from reference during the conversion of Switched-Capacitor ADC, results in fluctuation of reference voltage. For purpose of high integratin and low cost, high-speed high-resolution ADC needs to integrate reference buffer on-chip to obtain a stable reference voltage. Wide-band reference buffer is easy to integrate but it consumes a lot of power. F urthermore, wide-band buffer introduces extra noise and has poor Power Supply Rejection Ratio. The poor pow-efficent of wide-band buffer goes against low-power design, either. Narrow-band reference buffer has better performance on power consumption and noise than wide-band reference buffer. However, it needs a off-chip bypass capacitor, which needs more extra pins and results in larger packaging size. Parasitic inductance of bonding wire and dymanic charge injection caused by the switching of capacitor could cause resonate of reference voltage, extremely in the high-speed ADC. In order to maintain high precision of reference voltage, a lot of on-chip decoupling capacitors should be adopted to absorb charge, which means, narrow-band reference buffer also occupies large chip area. Therefore, narrow-band reference buffer could not satisfy the demand of SOC for easy integration. Low-power reference buffer used in high-speed high-resolution ADC becomes one of the key points to decide whether the ADC could be low-power and easily integrated.After analyzing and summarizing the existing reference buffers, a conclusion is made that low-power reference buffer is restricted by charge loss in reference voltage. Based on the quantitative analysis on loss charge in ADC reference voltage, a charge-compensation technique is adopted in reference voltage of high-speed switched ADC to diminish the area of on-chip decoupling capacitors in low-power narrow-band reference buffer. Different structures of ADCs are designed to verify the charge-compensation technique. First, charge-compensation circuit based on charge-compensation method for a 12-bit 500MS/s Pipelined ADC is designed. On-chip decoupling capacitor area diminishes when low-power narrow-band reference buffer is used and off-chip decoupling capacitor disused, which is verified in this thesis. Transistor-level simulation results show that SNDR and SFDR have 9d B and 12 d B improvement respectively when on-chip decoupling capacitor is only 170 p F, without off-chip decoupling capacitor and charge-compensation technique is used. Then, a 11-bit 200MS/s Subranged SAR ADC and its corresponding charge-compensation circuit are designed, layout design and post simulation are finished. Post simulation results show that SNDR and SFDR have 2d B and 14 d B improvement respectively when charge-compensation method is used. Finally, 11-bit 200MS/s Subranged SAR ADC with charge-compensation technique is designed and taped out. Charge-compensation circuit based on charge-compensation technique features in very low overhead of logic, area, and power. It can be used in all Swiched-Capacitor ADCs, too.