Research On The Design Of High Performance Redundant Binary Multipliers

The digital multiplier is one of the indispensable arithmetic units in digital signal processors, microprocessors and digital filter chips, which largely determines the performance of digital processors. It is desirable to use high-performance multipliers in processors.In this thesis, two kinds of digital multipliers, namely the redundant binary radix-4 Booth encoding(RBBE-2) multiplier and the redundant binary radix-16 Booth encoding(RBBE-4) multiplier are investigated and a new Booth encoding based on RBBE-4 is proposed. Similar to normal binary(NB) multipliers, an RB multiplier consists of three basic blocks: the RB partial product generator(PPG), RB partial product accumulator(RBPPA) and the RB-NB converter. Due to the carry-free feature, regular structure and interconnection of redundant binary adder, the partial products are accumulated in the format of redundant binary number during partial products accumulation stages.The radix-4 Booth encoding is widely used for PPG to reduce partial product numbers by half. Every two adjacent partial products constitute an RB number. An extra error-correcting word(ECW) is generated by both RB and Booth encodings. The addition of these partial products can be performed using n-1 RBPPA stages for 2n-b multipliers. The benefits of using high radix Booth encoders to reduce the number of partial products has been hampered by the complexity of generating the hard multiples. The proposed radix-16 encoding technique can removes hard multiples by the differences of two simple 2n multiples, which avoids the hard multiples of high-radix Booth encoding without any ECW. A new RB partial product generator based on RBBE-4 is also presented in this thesis. Compared with previous RBBE-2 multiplier and RBBE-4 multiplier, our proposed RBBE-4 generates the RB partial products faster in speed. The RBPPA are accumulated in the format of RB number. Finally, a RB-NB converter is used to convert the RB product to NB product.All the designs are described in Verilog HDL and synthesized by Synopsys Design Compiler. The results achieved with Artisan Nangate 45 nm standard-cell show that the proposed 8-b, 16-b and 32-b RB multipliers can reduce delay and area significantly. The RB multipliers designed with the proposed RBBE-4 partial product generator have on average 10.65% higher speed and 7.93% less area compared with previous multipliers.