Key Technologies Research On High Speed CMOS Time-interleaved SAR ADCs

Analog to digital converter(ADC)is one of the most essential components in current electronic systems.It converts the analog information to digital domain and has been widely used in wireless communication,optical communication,and image processing systems.With the development of microelectronics,especially with the technology scaling down,systems on chip(SoC)are shooting for higher frequency,lower power consumption.This requires high performance ADCs.Therefore,the study for high speed and low power ADC is of great importance for both industry and academic perspective.Compared to other high speed ADCs,time-interleaved(TI)ADCs could reach really high conversion speed.When the sub-channel employs successive approximation register(SAR)ADC,high power efficiency is available.By far,the study for TI-SAR ADC has facing the following challenges:1)How to overcome the influence of channel mismatches,including offset mismatch,gain mismatch,bandwidth mismatch and timing skew.Special attention should be paid for timing skew,which is the most critical one for TI ADC.2)How to realize high speed medium to high resolution sub-ADC,meaning high speed capacitor DAC switching and redundancy issues should be handled.3)How to realize low power ADC with certain conversion speed and resolution.In this paper,some key techniques of high speed high resolution TI-SAR ADC have been studied.The calibration for channel mismatches is achieved and the performance of the TI ADC has been improved.Through the analysis of channel mismatches,the model of mismatches has been realized in MATLAB.The relationship between ADC performance and mismatches has been drawn,which can be the guide for designing a TI ADC.Based on the analysis,a digital background calibration method for timing skew has been proposed.This method detects the sign of timing skew through the autocorrelation function of sub-ADC outputs.And then interpolation filters are adopted to compensate the wrong codes in digital domain.The proposed Lagrange differentiator has the merits of simple,low taps and low power.This calibration algorithm could effectively improve the SNDR of TI ADC with the bandwidth of(0,0.44)f_s and has the advantage of high convergence speed.Based on TSMC 65nm CMOS technology,a 10-bit 150MS/s SAR ADC with nonbinary searching algorithm has been realized.By inserting some redundancy,the DAC settling errors can be tolerance and thus improving the conversion speed.Split capacitor DAC switching is adopted to further increase the conversion speed and reduce the dynamic offset.Moreover,monotonic switching is employed in the LSB capacitor to reduce the whole area of capacitor array by half.Using the dynamic comparator and register can realize both high speed and low power.The full adder based encoder is used to convert the11-bit raw code to 10-bit binary code.The SAR ADC schematic circuits and layout have been completed.The chip area is 0.079mm~2 and power consumption is 1.4mW.With the sampling rate of 150MS/s,DNL is within-0.54/0.52 LSB and INL is within-1/0.9 LSB.With Nyquist input frequency,the SNDR and SFDR are 51.1 dB and 62.35dB,respectively,resulting in the FoM of 31.8fJ/conv.–step.Based on TSMC 65nm CMOS technology,a 10-bit four channel 600MS/s TI-SAR ADC has been realized.The sub-ADC employs the previous mentioned SAR ADC.The clock generator is based on dynamic register divider and transmission gate,which could lower the timing skew and jitter.Digital calibration methods are used to deal with the timing skew offset mismatch and gain mismatch.A high speed high accuracy sampling switch with body effect compensation has been proposed.The simulation results show that with variety of PVT conditions,all SFDRs are beyond 66dB.On-chip reference voltage generators(RVGs),which supply stable and high response reference voltages,are integrated for SAR ADC.The use of RVGs results in reduced on-chip decoupling capacitors.The prototype of this TI-SAR ADC has been measured.The chip area is0.69mm~2 and power consumption is 34mW.With the sampling rate of 600MS/s,DNL is within-0.21/0.39 LSB and INL is within-0.94/0.93 LSB.With input frequency of100MHz and after calibration,the SNDR,SFDR and ENOB are 52.1dB,56.4dB and8.36bit,respectively.With input frequency of 240MHz and after calibration,the SNDR is49dB and resulting in the FoM of 246fJ/conv.–step.The proposed TI-SAR ADC and calibration algorithm achieve the design requirement and reach the state-of-art compared to the existing TI ADCs.