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Design And Evaluation Of Redundant Binary Multipliers Based On Approximate Logic Design Tool

Posted on:2019-02-13Degree:MasterType:Thesis
Country:ChinaCandidate:T CaoFull Text:PDF
GTID:2428330596450060Subject:Circuits and Systems
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The reduction of IC technology size and integration density has brought a revolutionary change but power consumption is still one of the main factors in the development of Integrated Circuits.Approximate computing provides a new approach for low power design at the cost of accuracy.There are many fault-tolerant applications such as DSP,machine learning and pattern recognition which allow some errors but still achieve acceptable results.As the core component of the processor,power consumption of the multiplier is decisive for the processor performance.Compared to Normal Binary(NB)multipliers,Redundant Binary(RB)Multipliers have the advantage of carry-free feature.The design of approximate RB multiplier can improve system performance effectively.In this paper,we proposed an Approximate Logic Design(ALD)tool.The tool uses an error matrix to analyze the accuracy of the approximate designs,and the complexity is measured by calculating the Transistor Counts(TC).The proposed ALD tool gives the optimal approximate design under constraint conditions.Based on the stage of Partial Product(PP)generation,PP compression and the final product,we have designed two approximate Booth encoders,two approximate RB compressors and an approximate RB-NB converter by using the ALD tool,a scheme of approximate and exact regular PP array to meet different accuracy is designed.The approximate factor p is used to adjust the accuracy,and four approximate RB multipliers are designed with adjustable accuracy.The paper completed the evaluation and analysis the hardware complexity and the error metrics of RB multiplier from each module to the overall approximate design.The hardware design is written in Verilog HDL and the hardware performance is obtained through the Design Complier tool.The error analysis is obtained through C++ modeling.The test results show that the hardware performance of the 8×8-bit,16×16-bit,32×32-bit approximate RB multipliers are superior to the exact RB multiplier.The performance of the proposed RB multipliers is better than existing approximate multiplier,especially its delay and computing accuracy.Approximate RB multipliers are also applied to the application of image processing,FIR filter and K-means clustering.The results verified the reliability of the approximate RB multiplier and reinforced that the approximate multiplier can be effectively deployed in fault-tolerant applications.
Keywords/Search Tags:Approximate Computing, Approximate Logic Design (ALD), Redundant Binary (RB) Multiplier, Low Power, Fault-Tolerant Application
PDF Full Text Request
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